[llvm-commits] [llvm] r112983 - in /llvm/trunk/lib/Target/ARM: ARMExpandPseudoInsts.cpp ARMISelDAGToDAG.cpp ARMInstrNEON.td NEONPreAllocPass.cpp

[Jakob Stoklund Olesen]

On Sep 8, 2010, at 5:40 PM, Bob Wilson wrote:

>> This part is weird. Is OddDblSpc guaranteed to have DstReg live in? In that case, would there already be a DstReg<imp-use> operand on MI that gets transferred by TransferImpOps()?
>> 
>> The end result should be:
>> 
>> %D0, %D2, ... = VLD ..., %QQQQ0<imp-def>
>> %D1, %D3, ... = VLD ..., %QQQQ0<imp-use,kill>, %QQQQ0<imp-def>
>> 
> 
> The double-spaced VLD3/VLD4 instructions will have an explicit source operand for the super register.  (It is tied to the destination operand, so it will always be the same register at this point.)  The operand is basically being transferred from an explicit operand on the pseudo instruction to an implicit operand on the real instruction.  Because of that, we shouldn't have to worry about conflicts with arbitrary implicit operands.
> 
> As we discussed Friday, I also added the imp-use for both of the "even" and "odd" VLDs.

Thanks, it looks good to me.

The first load will get a %QQQQ0<imp-use,undef> operand which is pretty much a noop, but I think it is more robust this way.

/jakob

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