[llvm-commits] [llvm] r113406 - /llvm/trunk/lib/Target/X86/X86InstrMMX.td
Dale Johannesen
dalej at apple.com
Wed Sep 8 13:54:01 PDT 2010
Author: johannes
Date: Wed Sep 8 15:54:00 2010
New Revision: 113406
URL: http://llvm.org/viewvc/llvm-project?rev=113406&view=rev
Log:
Slight cleanup, use only one form of MMXI_binop_rm_int.
Modified:
llvm/trunk/lib/Target/X86/X86InstrMMX.td
Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=113406&r1=113405&r2=113406&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Wed Sep 8 15:54:00 2010
@@ -35,29 +35,13 @@
(load_mmx addr:$src2)))))]>;
}
- // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic.
- multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
- bit Commutable = 0> {
- def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
- (ins VR64:$src1, VR64:$src2),
- !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
- [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
- let isCommutable = Commutable;
- }
- def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
- (ins VR64:$src1, i64mem:$src2),
- !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
- [(set VR64:$dst, (IntId VR64:$src1,
- (bitconvert (load_mmx addr:$src2))))]>;
- }
-
- // MMXI_binop_rm_int2 - Simple MMX binary operator based on intrinsic, with a
+ // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic, with a
// different name for the generated instructions than MMXI_binop_rm uses.
- // Thus int2 and rm can coexist for different implementations of the same
- // instruction, while int and rm cannot. This is temporary during transition
- // to intrinsic-only implementation. When it is removed, remove the FIXME
- // from X86RecognizableInstr.cpp.
- multiclass MMXI_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId,
+ // Thus int and rm can coexist for different implementations of the same
+ // instruction. This is temporary during transition to intrinsic-only
+ // implementation; eventually the non-intrinsic forms will go away. When
+ // When this is cleaned up, remove the FIXME from X86RecognizableInstr.cpp.
+ multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
bit Commutable = 0> {
def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
(ins VR64:$src1, VR64:$src2),
@@ -211,13 +195,13 @@
// -- Addition
defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>,
- MMXI_binop_rm_int2<0xFC, "paddb", int_x86_mmx_padd_b, 1>;
+ MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b, 1>;
defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>,
- MMXI_binop_rm_int2<0xFD, "paddw", int_x86_mmx_padd_w, 1>;
+ MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w, 1>;
defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>,
- MMXI_binop_rm_int2<0xFE, "paddd", int_x86_mmx_padd_d, 1>;
+ MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d, 1>;
defm MMX_PADDQ : MMXI_binop_rm<0xD4, "paddq", add, v1i64, 1>,
- MMXI_binop_rm_int2<0xD4, "paddq", int_x86_mmx_padd_q, 1>;
+ MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q, 1>;
defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>;
defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
@@ -226,13 +210,13 @@
// -- Subtraction
defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>,
- MMXI_binop_rm_int2<0xF8, "psubb", int_x86_mmx_psub_b>;
+ MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b>;
defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>,
- MMXI_binop_rm_int2<0xF9, "psubw", int_x86_mmx_psub_w>;
+ MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w>;
defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>,
- MMXI_binop_rm_int2<0xFA, "psubd", int_x86_mmx_psub_d>;
+ MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d>;
defm MMX_PSUBQ : MMXI_binop_rm<0xFB, "psubq", sub, v1i64>,
- MMXI_binop_rm_int2<0xFB, "psubq", int_x86_mmx_psub_q>;
+ MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q>;
defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
@@ -242,7 +226,7 @@
// -- Multiplication
defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>,
- MMXI_binop_rm_int2<0xD5, "pmullw", int_x86_mmx_pmull_w, 1>;
+ MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w, 1>;
defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>;
defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>;
@@ -264,12 +248,12 @@
// Logical Instructions
defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>,
- MMXI_binop_rm_int2<0xDB, "pand", int_x86_mmx_pand, 1>;
+ MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand, 1>;
defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>,
- MMXI_binop_rm_int2<0xEB, "por" , int_x86_mmx_por, 1>;
+ MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por, 1>;
defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>,
- MMXI_binop_rm_int2<0xEF, "pxor", int_x86_mmx_pxor, 1>;
-defm MMX_PANDN : MMXI_binop_rm_int2<0xDF, "pandn", int_x86_mmx_pandn, 1>;
+ MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor, 1>;
+defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn, 1>;
let Constraints = "$src1 = $dst" in {
def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
@@ -397,17 +381,17 @@
(v2i32 (mmx_unpckl VR64:$src1,
(bc_v2i32 (load_mmx addr:$src2)))))]>;
}
-defm MMX_PUNPCKHBW : MMXI_binop_rm_int2<0x68, "punpckhbw",
+defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw",
int_x86_mmx_punpckhbw>;
-defm MMX_PUNPCKHWD : MMXI_binop_rm_int2<0x69, "punpckhwd",
+defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd",
int_x86_mmx_punpckhwd>;
-defm MMX_PUNPCKHDQ : MMXI_binop_rm_int2<0x6A, "punpckhdq",
+defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq",
int_x86_mmx_punpckhdq>;
-defm MMX_PUNPCKLBW : MMXI_binop_rm_int2<0x60, "punpcklbw",
+defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw",
int_x86_mmx_punpcklbw>;
-defm MMX_PUNPCKLWD : MMXI_binop_rm_int2<0x61, "punpcklwd",
+defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd",
int_x86_mmx_punpcklwd>;
-defm MMX_PUNPCKLDQ : MMXI_binop_rm_int2<0x62, "punpckldq",
+defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq",
int_x86_mmx_punpckldq>;
// -- Pack Instructions
@@ -723,30 +707,30 @@
// Patterns for vector comparisons
def : Pat<(v8i8 (X86pcmpeqb VR64:$src1, VR64:$src2)),
- (MMX_PCMPEQBrr VR64:$src1, VR64:$src2)>;
+ (MMX_PCMPEQBirr VR64:$src1, VR64:$src2)>;
def : Pat<(v8i8 (X86pcmpeqb VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
- (MMX_PCMPEQBrm VR64:$src1, addr:$src2)>;
+ (MMX_PCMPEQBirm VR64:$src1, addr:$src2)>;
def : Pat<(v4i16 (X86pcmpeqw VR64:$src1, VR64:$src2)),
- (MMX_PCMPEQWrr VR64:$src1, VR64:$src2)>;
+ (MMX_PCMPEQWirr VR64:$src1, VR64:$src2)>;
def : Pat<(v4i16 (X86pcmpeqw VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
- (MMX_PCMPEQWrm VR64:$src1, addr:$src2)>;
+ (MMX_PCMPEQWirm VR64:$src1, addr:$src2)>;
def : Pat<(v2i32 (X86pcmpeqd VR64:$src1, VR64:$src2)),
- (MMX_PCMPEQDrr VR64:$src1, VR64:$src2)>;
+ (MMX_PCMPEQDirr VR64:$src1, VR64:$src2)>;
def : Pat<(v2i32 (X86pcmpeqd VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
- (MMX_PCMPEQDrm VR64:$src1, addr:$src2)>;
+ (MMX_PCMPEQDirm VR64:$src1, addr:$src2)>;
def : Pat<(v8i8 (X86pcmpgtb VR64:$src1, VR64:$src2)),
- (MMX_PCMPGTBrr VR64:$src1, VR64:$src2)>;
+ (MMX_PCMPGTBirr VR64:$src1, VR64:$src2)>;
def : Pat<(v8i8 (X86pcmpgtb VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
- (MMX_PCMPGTBrm VR64:$src1, addr:$src2)>;
+ (MMX_PCMPGTBirm VR64:$src1, addr:$src2)>;
def : Pat<(v4i16 (X86pcmpgtw VR64:$src1, VR64:$src2)),
- (MMX_PCMPGTWrr VR64:$src1, VR64:$src2)>;
+ (MMX_PCMPGTWirr VR64:$src1, VR64:$src2)>;
def : Pat<(v4i16 (X86pcmpgtw VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
- (MMX_PCMPGTWrm VR64:$src1, addr:$src2)>;
+ (MMX_PCMPGTWirm VR64:$src1, addr:$src2)>;
def : Pat<(v2i32 (X86pcmpgtd VR64:$src1, VR64:$src2)),
- (MMX_PCMPGTDrr VR64:$src1, VR64:$src2)>;
+ (MMX_PCMPGTDirr VR64:$src1, VR64:$src2)>;
def : Pat<(v2i32 (X86pcmpgtd VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
- (MMX_PCMPGTDrm VR64:$src1, addr:$src2)>;
+ (MMX_PCMPGTDirm VR64:$src1, addr:$src2)>;
// CMOV* - Used to implement the SELECT DAG operation. Expanded after
// instruction selection into a branch sequence.
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