[llvm-commits] [llvm] r110576 - in /llvm/trunk: lib/Target/CellSPU/SPUISelLowering.cpp lib/Target/CellSPU/SPUISelLowering.h lib/Target/CellSPU/SPUInstrInfo.td lib/Target/CellSPU/SPUNodes.td lib/Target/CellSPU/SPURegisterInfo.cpp test/CodeGen/CellSP...

[Bob Wilson]

On Aug 11, 2010, at 4:19 AM, Kalle.Raiskila at nokia.com wrote:

> On Tue, 2010-08-10 at 19:12 +0200, Bob Wilson wrote:
>> On Aug 10, 2010, at 3:53 AM, Kalle.Raiskila at nokia.com wrote:
>>> b) to the best of my understanding, v2i32 has to be legal if it is to be
>>> used in return values and function parameters.
>> 
>> The types of return values and function parameters are also legalized.  If you pass an argument with a non-legal type, it should be promoted or expanded to make it legal.
> 
> The problem here was that v2i32 gets expanded to two i32s instead of
> promoted to one v4i32. Is it possible to force promotion somehow?

The following code from TargetLowering::computeRegisterProperties() suggests that promotion should be the default:

    // Determine if there is a legal wider type.
    bool IsLegalWiderType = false;
    EVT EltVT = VT.getVectorElementType();
    unsigned NElts = VT.getVectorNumElements();
    for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
      EVT SVT = (MVT::SimpleValueType)nVT;
      if (isTypeSynthesizable(SVT) && SVT.getVectorElementType() == EltVT &&
          SVT.getVectorNumElements() > NElts && NElts != 1) {
        TransformToType[i] = SVT;
        ValueTypeActions.setTypeAction(VT, Promote);
        IsLegalWiderType = true;
        break;
      }
    }

If that's not happening, you might want to step through that code and see why not.  Otherwise, you can specify promote vs. expand for each operation via TargetLowering::setOperationAction().

> 
> 
>> 
>> But, if your target doesn't have any scalar
>> 32-bit registers, passing i32 arguments is going to be a pretty
>> "interesting" regardless....
> 
> This is indeed the case. SPU's native wordlength is 32, but all general
> purpose registers are 4-way vectors (128bit). And all instructions are
> SIMD vector instructions. Where i32s are needed (e.g. memory address)
> only the first slot of the vector register is used. This is the way i32s
> are "emulated" in the SPU backend. And this is how I tried to "emulate"
> v2i32s too.
> 
> "Interesting", eih? :)

Ugh.  I expect you'll have to fight against a lot of implicit assumptions that i32 is legal.  Good luck....