[llvm-commits] [llvm] r110798 - in /llvm/trunk: lib/Target/ARM/ARM.td lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMSubtarget.h lib/Target/ARM/ARMTargetMachine.cpp test/CodeGen/ARM/div.ll test/CodeGen/Thumb2/div.ll
Evan Cheng
evan.cheng at apple.com
Wed Aug 11 00:17:47 PDT 2010
Author: evancheng
Date: Wed Aug 11 02:17:46 2010
New Revision: 110798
URL: http://llvm.org/viewvc/llvm-project?rev=110798&view=rev
Log:
Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors.
Modified:
llvm/trunk/lib/Target/ARM/ARM.td
llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
llvm/trunk/lib/Target/ARM/ARMSubtarget.h
llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
llvm/trunk/test/CodeGen/ARM/div.ll
llvm/trunk/test/CodeGen/Thumb2/div.ll
Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=110798&r1=110797&r2=110798&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Wed Aug 11 02:17:46 2010
@@ -28,6 +28,8 @@
"Enable NEON instructions">;
def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
"Enable Thumb2 instructions">;
+def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
+ "Does not support ARM mode execution">;
def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
"Enable half-precision floating point">;
def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
@@ -69,7 +71,7 @@
"ARM v6">;
def ArchV6M : SubtargetFeature<"v6m", "ARMArchVersion", "V6M",
"ARM v6m",
- [FeatureDB]>;
+ [FeatureNoARM, FeatureDB]>;
def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
"ARM v6t2",
[FeatureThumb2]>;
@@ -78,7 +80,8 @@
[FeatureThumb2, FeatureNEON, FeatureDB]>;
def ArchV7M : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
"ARM v7M",
- [FeatureThumb2, FeatureDB, FeatureHWDiv]>;
+ [FeatureThumb2, FeatureNoARM, FeatureDB,
+ FeatureHWDiv]>;
//===----------------------------------------------------------------------===//
// ARM Processors supported.
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=110798&r1=110797&r2=110798&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Wed Aug 11 02:17:46 2010
@@ -36,6 +36,7 @@
, SlowFPBrcc(false)
, IsThumb(isT)
, ThumbMode(Thumb1)
+ , NoARM(false)
, PostRAScheduler(false)
, IsR9Reserved(ReserveR9)
, UseMovt(UseMOVT)
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=110798&r1=110797&r2=110798&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Wed Aug 11 02:17:46 2010
@@ -63,6 +63,9 @@
/// ThumbMode - Indicates supported Thumb version.
ThumbTypeEnum ThumbMode;
+ /// NoARM - True if subtarget does not support ARM mode execution.
+ bool NoARM;
+
/// PostRAScheduler - True if using post-register-allocation scheduler.
bool PostRAScheduler;
@@ -136,6 +139,8 @@
bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; }
bool hasV7Ops() const { return ARMArchVersion >= V7A; }
+ bool hasARMOps() const { return !NoARM; }
+
bool hasVFP2() const { return ARMFPUType >= VFPv2; }
bool hasVFP3() const { return ARMFPUType >= VFPv3; }
bool hasNEON() const { return ARMFPUType >= NEON; }
Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=110798&r1=110797&r2=110798&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Wed Aug 11 02:17:46 2010
@@ -65,6 +65,9 @@
"v128:64:128-v64:64:64-n32")),
TLInfo(*this),
TSInfo(*this) {
+ if (!Subtarget.hasARMOps())
+ report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
+ "support ARM mode execution!");
}
ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
Modified: llvm/trunk/test/CodeGen/ARM/div.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/div.ll?rev=110798&r1=110797&r2=110798&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/div.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/div.ll Wed Aug 11 02:17:46 2010
@@ -1,13 +1,9 @@
; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=CHECK-ARM
-; RUN: llc < %s -march=arm -mcpu=cortex-m3 \
-; RUN: | FileCheck %s -check-prefix=CHECK-ARMV7M
define i32 @f1(i32 %a, i32 %b) {
entry:
; CHECK-ARM: f1
; CHECK-ARM: __divsi3
-; CHECK-ARMV7M: f1
-; CHECK-ARMV7M: sdiv
%tmp1 = sdiv i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
}
@@ -16,8 +12,6 @@
entry:
; CHECK-ARM: f2
; CHECK-ARM: __udivsi3
-; CHECK-ARMV7M: f2
-; CHECK-ARMV7M: udiv
%tmp1 = udiv i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
}
@@ -26,8 +20,6 @@
entry:
; CHECK-ARM: f3
; CHECK-ARM: __modsi3
-; CHECK-ARMV7M: f3
-; CHECK-ARMV7M: sdiv
%tmp1 = srem i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
}
@@ -36,8 +28,6 @@
entry:
; CHECK-ARM: f4
; CHECK-ARM: __umodsi3
-; CHECK-ARMV7M: f4
-; CHECK-ARMV7M: udiv
%tmp1 = urem i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
}
Modified: llvm/trunk/test/CodeGen/Thumb2/div.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/div.ll?rev=110798&r1=110797&r2=110798&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/div.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/div.ll Wed Aug 11 02:17:46 2010
@@ -1,6 +1,6 @@
; RUN: llc < %s -march=thumb -mattr=+thumb2 \
; RUN: | FileCheck %s -check-prefix=CHECK-THUMB
-; RUN: llc < %s -march=arm -mcpu=cortex-m3 -mattr=+thumb2 \
+; RUN: llc < %s -march=thumb -mcpu=cortex-m3 -mattr=+thumb2 \
; RUN: | FileCheck %s -check-prefix=CHECK-THUMBV7M
define i32 @f1(i32 %a, i32 %b) {
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