[llvm-commits] [llvm] r109985 - in /llvm/trunk: lib/Target/Alpha/AlphaISelDAGToDAG.cpp test/CodeGen/Alpha/2010-08-01-mulreduce64.ll

Eli Friedman eli.friedman at gmail.com
Sun Aug 1 14:13:28 PDT 2010


Author: efriedma
Date: Sun Aug  1 16:13:28 2010
New Revision: 109985

URL: http://llvm.org/viewvc/llvm-project?rev=109985&view=rev
Log:
PR7774: Fix undefined shifts in Alpha backend.  As a bonus, this actually
improves the generated code in some cases.


Added:
    llvm/trunk/test/CodeGen/Alpha/2010-08-01-mulreduce64.ll
Modified:
    llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp?rev=109985&r1=109984&r2=109985&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Sun Aug  1 16:13:28 2010
@@ -113,8 +113,8 @@
     static uint64_t getNearPower2(uint64_t x) {
       if (!x) return 0;
       unsigned at = CountLeadingZeros_64(x);
-      uint64_t complow = 1 << (63 - at);
-      uint64_t comphigh = 1 << (64 - at);
+      uint64_t complow = 1ULL << (63 - at);
+      uint64_t comphigh = 1ULL << (64 - at);
       //cerr << x << ":" << complow << ":" << comphigh << "\n";
       if (abs64(complow - x) <= abs64(comphigh - x))
         return complow;

Added: llvm/trunk/test/CodeGen/Alpha/2010-08-01-mulreduce64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Alpha/2010-08-01-mulreduce64.ll?rev=109985&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Alpha/2010-08-01-mulreduce64.ll (added)
+++ llvm/trunk/test/CodeGen/Alpha/2010-08-01-mulreduce64.ll Sun Aug  1 16:13:28 2010
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=alpha | FileCheck %s
+
+define fastcc i64 @getcount(i64 %s) {
+	%tmp431 = mul i64 %s, 12884901888
+	ret i64 %tmp431
+}
+
+; CHECK: sll $16,33,$0
+; CHECK-NEXT: sll $16,32,$1
+; CHECK-NEXT: addq $0,$1,$0
+





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