[llvm-commits] [llvm] r109842 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/ARMRegisterInfo.td lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h lib/Target/ARM/Thumb2InstrInfo.cpp test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll test/CodeGen/Thumb2/thumb2-badreg-operands.ll utils/TableGen/EDEmitter.cpp

[Jakob Stoklund Olesen]

On Jul 29, 2010, at 7:41 PM, Jim Grosbach wrote:
> This patch adds a new register class for use by Thumb2 that excludes
> the problematic registers (SP and PC) and is used instead of GPR
> for those operands which cannot legally reference PC or SP. The
> trivial coalescer explicitly requires that the register class
> of the destination for the COPY instruction contain the source
> register for the COPY to be considered for coalescing. This prevents
> errant instructions like that above.

Thanks, Jim. This is awesome.

It is really important that target instruction descriptors accurately model the instruction constraints. It lets us do more target independent optimizations.

> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=109842&r1=109841&r2=109842&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Jul 29 21:41:01 2010
> @@ -721,8 +721,9 @@
>                             Align);
> 
>   // tGPR is used sometimes in ARM instructions that need to avoid using
> -  // certain registers.  Just treat it as GPR here.
> -  if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass)
> +  // certain registers.  Just treat it as GPR here. Likewise, rGPR.
> +  if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
> +      || RC == ARM::rGPRRegisterClass)
>     RC = ARM::GPRRegisterClass;

This should be folded into the switch below:

>   switch (RC->getID()) {

/jakob

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