[llvm-commits] [llvm] r109079 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

[Evan Cheng]

Author: evancheng
Date: Thu Jul 22 00:18:41 2010
New Revision: 109079

URL: http://llvm.org/viewvc/llvm-project?rev=109079&view=rev
Log:
Initialize RegLimit only when register pressure is being tracked.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=109079&r1=109078&r2=109079&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu Jul 22 00:18:41 2010
@@ -1036,7 +1036,7 @@
     std::vector<SUnit*> Queue;
     SF Picker;
     unsigned CurQueueId;
-    bool isBottomUp;
+    bool TracksRegPressure;
 
   protected:
     // SUnits - The SUnits for the current graph.
@@ -1061,20 +1061,22 @@
 
   public:
     RegReductionPriorityQueue(MachineFunction &mf,
-                              bool isbottomup,
+                              bool tracksrp,
                               const TargetInstrInfo *tii,
                               const TargetRegisterInfo *tri,
                               const TargetLowering *tli)
-      : Picker(this), CurQueueId(0), isBottomUp(isbottomup),
+      : Picker(this), CurQueueId(0), TracksRegPressure(tracksrp),
         MF(mf), TII(tii), TRI(tri), TLI(tli), scheduleDAG(NULL) {
-      unsigned NumRC = TRI->getNumRegClasses();
-      RegLimit.resize(NumRC);
-      RegPressure.resize(NumRC);
-      std::fill(RegLimit.begin(), RegLimit.end(), 0);
-      std::fill(RegPressure.begin(), RegPressure.end(), 0);
-      for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
-             E = TRI->regclass_end(); I != E; ++I)
-        RegLimit[(*I)->getID()] = tri->getAllocatableSet(MF, *I).count() - 1;
+      if (TracksRegPressure) {
+        unsigned NumRC = TRI->getNumRegClasses();
+        RegLimit.resize(NumRC);
+        RegPressure.resize(NumRC);
+        std::fill(RegLimit.begin(), RegLimit.end(), 0);
+        std::fill(RegPressure.begin(), RegPressure.end(), 0);
+        for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
+               E = TRI->regclass_end(); I != E; ++I)
+          RegLimit[(*I)->getID()] = tri->getAllocatableSet(MF, *I).count() - 1;
+      }
     }
     
     void initNodes(std::vector<SUnit> &sunits) {
@@ -1207,7 +1209,10 @@
       return false;
     }
 
-    void OpenPredLives(SUnit *SU) {
+    void ScheduledNode(SUnit *SU) {
+      if (!TracksRegPressure)
+        return;
+
       const SDNode *N = SU->getNode();
       if (!N->isMachineOpcode())
         return;
@@ -1260,9 +1265,14 @@
         else
           RegPressure[RCId] -= TLI->getRepRegClassCostFor(VT);
       }
+
+      dumpRegPressure();
     }
 
-    void ClosePredLives(SUnit *SU) {
+    void UnscheduledNode(SUnit *SU) {
+      if (!TracksRegPressure)
+        return;
+
       const SDNode *N = SU->getNode();
       if (!N->isMachineOpcode())
         return;
@@ -1317,19 +1327,7 @@
         unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
         RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
       }
-    }
 
-    void ScheduledNode(SUnit *SU) {
-      if (!TLI || !isBottomUp)
-        return;
-      OpenPredLives(SU);
-      dumpRegPressure();
-    }
-
-    void UnscheduledNode(SUnit *SU) {
-      if (!TLI || !isBottomUp)
-        return;
-      ClosePredLives(SU);
       dumpRegPressure();
     }
 
@@ -1851,7 +1849,7 @@
   const TargetRegisterInfo *TRI = TM.getRegisterInfo();
   
   BURegReductionPriorityQueue *PQ =
-    new BURegReductionPriorityQueue(*IS->MF, true, TII, TRI, 0);
+    new BURegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0);
   ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, false, PQ);
   PQ->setScheduleDAG(SD);
   return SD;  
@@ -1877,7 +1875,7 @@
   const TargetRegisterInfo *TRI = TM.getRegisterInfo();
   
   SrcRegReductionPriorityQueue *PQ =
-    new SrcRegReductionPriorityQueue(*IS->MF, true, TII, TRI, 0);
+    new SrcRegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0);
   ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, false, PQ);
   PQ->setScheduleDAG(SD);
   return SD;