[llvm-commits] [llvm] r108991 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp lib/CodeGen/SelectionDAG/TargetLowering.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/PIC16/PIC16ISelLowering.cpp lib/Target/PIC16/PIC16ISelLowering.h

[Evan Cheng]

On Jul 21, 2010, at 9:39 AM, Jakob Stoklund Olesen wrote:

> 
> On Jul 20, 2010, at 11:09 PM, Evan Cheng wrote:
> 
>> +  case MVT::f32:
>> +    RRC = ARM::SPRRegisterClass;
>> +    break;
>> +  case MVT::f64: case MVT::v8i8: case MVT::v4i16:
>> +  case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
>> +    RRC = ARM::SPRRegisterClass;
>> +    Cost = 2;
>> +    break;
>> +  case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
>> +  case MVT::v4f32: case MVT::v2f64:
>> +    RRC = ARM::SPRRegisterClass;
>> +    Cost = 4;
>> +    break;
>> +  case MVT::v4i64:
>> +    RRC = ARM::SPRRegisterClass;
>> +    Cost = 8;
>> +    break;
>> +  case MVT::v8i64:
>> +    RRC = ARM::SPRRegisterClass;
>> +    Cost = 16;
>> +    break;
>>  }
>> +  return std::make_pair(RRC, Cost);
> 
> Nice!
> 
> Of course ARM is still being evil because there are 32 SPRs and 32 DPRs ;-)

There is no good way to model it. :-( I think using DPR as representative and cost 1 for both f32 and f64 is probably slightly more accurate.

Evan
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20100721/ab058f5d/attachment.html>