[llvm-commits] [llvm] r108816 - in /llvm/trunk: lib/Target/Mips/MipsISelLowering.cpp test/CodeGen/Mips/2010-07-20-Select.ll

[Jakob Stoklund Olesen]

On Jul 20, 2010, at 11:28 AM, Bruno Cardoso Lopes wrote:

> It seems ok to me, MipsISD::SelectCC has operand 2 as true and operand
> 3 as false,
> am I missing something?

No, it is probably fine.

I just noticed that the mapping between getOperand(2/3) and thisMBB/copy0MBB is swapped in the code, but it is not swapped in the comment.

It sounds like the comment was correct before, but the code was wrong. Now both are correct.

>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
>>> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Jul 20 02:58:51 2010
>>> @@ -317,13 +317,13 @@
>>>     BB->addSuccessor(sinkMBB);
>>> 
>>>     //  sinkMBB:
>>> -    //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
>>> +    //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
>>>     //  ...
>>>     BB = sinkMBB;
>>>     BuildMI(*BB, BB->begin(), dl,
>>>             TII->get(Mips::PHI), MI->getOperand(0).getReg())
>>> -      .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
>>> -      .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
>>> +      .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
>>> +      .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB);
>>> 
>>>     MI->eraseFromParent();   // The pseudo instruction is gone now.
>>>     return BB;