[llvm-commits] [llvm] r108735 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/TargetLowering.cpp

[Jakob Stoklund Olesen]

On Jul 19, 2010, at 3:25 PM, Eric Christopher wrote:

> 
> On Jul 19, 2010, at 3:22 PM, Jakob Stoklund Olesen wrote:
> 
>> 
>> On Jul 19, 2010, at 3:09 PM, Evan Cheng wrote:
>> 
>>> 
>>> On Jul 19, 2010, at 1:22 PM, Jakob Stoklund Olesen wrote:
>>>> 
>>>> Can you use some kind of scaling so a DPR counts as 0.5 QPR?
>>>> 
>>> 
>>> No, I don't like that. I was hoping to avoid having targets provide findRepresentativeClass(). But I think it cannot be avoided.
>> 
>> I don't think overriding findRepresentativeClass() solves the problem. There is no 'correct' representative register class.
>> 
>> Whenever you allocate a QPR, you block two DPRs.
>> Whenever you allocate a DPR, you block one (half) QPR.
>> 
>> I think you need to model that asymmetry somehow.
>> 
> 
> As a first pass for scheduling wouldn't the second one be a bit overkill?  i.e. is there anything wrong with considering it as a full QPR?  If so, just round up?

QPR has 16 registers, DPR has 32.

If each DPR counts as a QPR, the scheduler is going to behave as if there were only 16 DPR registers available. That is almost as bad as scheduling purely for register pressure.