[llvm-commits] [llvm] r108639 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Chris Lattner]

On Jul 18, 2010, at 1:47 AM, Owen Anderson wrote:

> Author: resistor
> Date: Sun Jul 18 03:47:54 2010
> New Revision: 108639
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=108639&view=rev
> Log:
> Add a DAGCombine xform to fold away redundant float->double->float conversions around sqrt instructions.
> I am assured by people more knowledgeable than me that there are no rounding issues in eliminating this.
> 
> This fixed <rdar://problem/8197504>.

Why a dag combine?  I thought that instcombine or simplifylibcalls already did this?  Doing this in the optimizer exposes other opportunities (e.g. when it is cross-block).

-Chris

> 
> Modified:
>    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> 
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=108639&r1=108638&r2=108639&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Jul 18 03:47:54 2010
> @@ -4926,6 +4926,19 @@
>     return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
>                        Tmp, N0.getOperand(1));
>   }
> +  
> +  // (f32 fp_round (f64 sqrt (f64 fp_extend (f32)))) -> (f32 sqrt)
> +  EVT VT0 = N0.getValueType();
> +  if (VT == MVT::f32 &&
> +      N0.getOpcode() == ISD::FSQRT && VT0 == MVT::f64) {
> +    SDValue N1 = N0.getOperand(0);
> +    EVT VT1 = N1.getValueType();
> +    if (N1.getOpcode() == ISD::FP_EXTEND && VT1 == MVT::f64 &&
> +        N1.getOperand(0).getValueType() == MVT::f32) {
> +      return DAG.getNode(ISD::FSQRT, N->getDebugLoc(), MVT::f32,
> +                         N1.getOperand(0), N->getOperand(1));
> +    }
> +  }
> 
>   return SDValue();
> }
> 
> 
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