[llvm-commits] [llvm] r107941 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll test/CodeGen/ARM/reg_sequence.ll

[Bob Wilson]

Author: bwilson
Date: Thu Jul  8 19:38:12 2010
New Revision: 107941

URL: http://llvm.org/viewvc/llvm-project?rev=107941&view=rev
Log:
Reenable DAG combining for vector shuffles.  It looks like it was temporarily
disabled and then never turned back on again.  Adjust some tests, one because
this change avoids an unnecessary instruction, and the other to make it
continue testing what it was intended to test.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll
    llvm/trunk/test/CodeGen/ARM/reg_sequence.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=107941&r1=107940&r2=107941&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jul  8 19:38:12 2010
@@ -6309,8 +6309,6 @@
 }
 
 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
-  return SDValue();
-  
   EVT VT = N->getValueType(0);
   unsigned NumElts = VT.getVectorNumElements();
 

Modified: llvm/trunk/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll?rev=107941&r1=107940&r2=107941&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll Thu Jul  8 19:38:12 2010
@@ -4,19 +4,22 @@
 
 ; This tests the fast register allocator's handling of partial redefines:
 ;
-;	%reg1026<def> = VMOVv16i8 0, pred:14, pred:%reg0
-;	%reg1028:dsub_1<def> = EXTRACT_SUBREG %reg1026<kill>, 1
+;      %reg1028:dsub_0<def>, %reg1028:dsub_1<def> = VLD1q64 %reg1025...
+;      %reg1030:dsub_1<def> = COPY %reg1028:dsub_0<kill>
 ;
-; %reg1026 gets allocated %Q0, and if %reg1028 is reloaded for the partial redef,
-; it cannot also get %Q0.
+; %reg1028 gets allocated %Q0, and if %reg1030 is reloaded for the partial
+; redef, it cannot also get %Q0.
 
-; CHECK: vmov.i8 q0, #0x0
-; CHECK-NOT: vld1.64 {d0,d1}
+; CHECK: vld1.64 {d0, d1}, [r0]
+; CHECK-NOT: vld1.64 {d0, d1}
 ; CHECK: vmov.f64 d3, d0
 
-define i32 @main(i32 %argc, i8** %argv) nounwind {
+define i32 @test(i8* %arg) nounwind {
 entry:
- %0 = shufflevector <2 x i64> undef, <2 x i64> zeroinitializer, <2 x i32> <i32 1, i32 2> ; <<2 x i64>> [#uses=1]
- store <2 x i64> %0, <2 x i64>* undef, align 16
+ %0 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %arg)
+ %1 = shufflevector <2 x i64> undef, <2 x i64> %0, <2 x i32> <i32 1, i32 2>
+ store <2 x i64> %1, <2 x i64>* undef, align 16
  ret i32 undef
 }
+
+declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*) nounwind readonly

Modified: llvm/trunk/test/CodeGen/ARM/reg_sequence.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/reg_sequence.ll?rev=107941&r1=107940&r2=107941&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/reg_sequence.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/reg_sequence.ll Thu Jul  8 19:38:12 2010
@@ -270,7 +270,6 @@
 entry:
 ; CHECK: t10:
 ; CHECK: vmov.i32 q1, #0x3F000000
-; CHECK: vdup.32 q0, d0[0]
 ; CHECK: vmov d0, d1
 ; CHECK: vmla.f32 q0, q0, d0[0]
   %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]