[llvm-commits] [llvm] r107750 - in /llvm/trunk/lib/Target/X86: X86Instr64bit.td X86InstrSSE.td

[Bruno Cardoso Lopes]

Author: bruno
Date: Tue Jul  6 20:43:01 2010
New Revision: 107750

URL: http://llvm.org/viewvc/llvm-project?rev=107750&view=rev
Log:
Use only one multiclass to pinsrq instructions

Modified:
    llvm/trunk/lib/Target/X86/X86Instr64bit.td
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=107750&r1=107749&r2=107750&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Tue Jul  6 20:43:01 2010
@@ -2349,27 +2349,3 @@
                         "movq\t{$src, $dst|$dst, $src}",
                         [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
 
-//===----------------------------------------------------------------------===//
-// X86-64 SSE4.1 Instructions
-//===----------------------------------------------------------------------===//
-
-let Constraints = "$src1 = $dst" in {
-  multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
-    def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
-                   (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
-                   !strconcat(OpcodeStr, 
-                    "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
-                   [(set VR128:$dst, 
-                     (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
-                   OpSize, REX_W;
-    def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
-                   (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
-                   !strconcat(OpcodeStr,
-                    "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
-                   [(set VR128:$dst, 
-                     (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
-                                       imm:$src3)))]>, OpSize, REX_W;
-  }
-} // Constraints = "$src1 = $dst"
-
-defm PINSRQ      : SS41I_insert64<0x22, "pinsrq">;

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107750&r1=107749&r2=107750&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jul  6 20:43:01 2010
@@ -4214,25 +4214,31 @@
 let Constraints = "$src1 = $dst" in
   defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
 
-multiclass SS41I_insert64_avx<bits<8> opc, string OpcodeStr> {
+multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
   def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
-                 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
-                 !strconcat(OpcodeStr, 
-                  "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
-                 [(set VR128:$dst, 
-                   (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
-                 OpSize, REX_W;
+      (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
+      !if(Is2Addr,
+        !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+        !strconcat(asm,
+                   "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+      [(set VR128:$dst,
+        (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
+      OpSize;
   def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
-                 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
-                 !strconcat(OpcodeStr,
-                  "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
-                 [(set VR128:$dst, 
-                   (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
-                                     imm:$src3)))]>, OpSize, REX_W;
+      (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
+      !if(Is2Addr,
+        !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+        !strconcat(asm,
+                   "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+      [(set VR128:$dst,
+        (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
+                          imm:$src3)))]>, OpSize;
 }
 
 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in
-  defm VPINSRQ : SS41I_insert64_avx<0x22, "vpinsrq">, VEX_4V, VEX_W;
+  defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
+let Constraints = "$src1 = $dst" in
+  defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
 
 // insertps has a few different modes, there's the first two here below which
 // are optimized inserts that won't zero arbitrary elements in the destination