[llvm-commits] [llvm] r107744 - in /llvm/trunk/lib/CodeGen: LiveIntervalAnalysis.cpp LowerSubregs.cpp ProcessImplicitDefs.cpp RegisterCoalescer.cpp SimpleRegisterCoalescing.cpp StackSlotColoring.cpp TwoAddressInstructionPass.cpp
Jakob Stoklund Olesen
stoklund at 2pi.dk
Tue Jul 6 17:32:25 PDT 2010
Author: stoklund
Date: Tue Jul 6 19:32:25 2010
New Revision: 107744
URL: http://llvm.org/viewvc/llvm-project?rev=107744&view=rev
Log:
Revert "Remove references to INSERT_SUBREG after de-SSA" r107725.
Buildbot breakage.
Modified:
llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
llvm/trunk/lib/CodeGen/LowerSubregs.cpp
llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp
llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
llvm/trunk/lib/CodeGen/StackSlotColoring.cpp
llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=107744&r1=107743&r2=107744&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Tue Jul 6 19:32:25 2010
@@ -324,6 +324,12 @@
if (mi->isCopyLike() ||
tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
CopyMI = mi;
+
+ // Some of the REG_SEQUENCE lowering in TwoAddressInstrPass creates
+ // implicit defs without really knowing. It shows up as INSERT_SUBREG
+ // using an undefined register.
+ if (mi->isInsertSubreg())
+ mi->getOperand(1).setIsUndef();
}
VNInfo *ValNo = interval.getNextValue(defIndex, CopyMI, true,
Modified: llvm/trunk/lib/CodeGen/LowerSubregs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LowerSubregs.cpp?rev=107744&r1=107743&r2=107744&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LowerSubregs.cpp (original)
+++ llvm/trunk/lib/CodeGen/LowerSubregs.cpp Tue Jul 6 19:32:25 2010
@@ -54,6 +54,7 @@
private:
bool LowerExtract(MachineInstr *MI);
+ bool LowerInsert(MachineInstr *MI);
bool LowerSubregToReg(MachineInstr *MI);
bool LowerCopy(MachineInstr *MI);
@@ -237,6 +238,90 @@
return true;
}
+bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
+ MachineBasicBlock *MBB = MI->getParent();
+ assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
+ (MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) &&
+ (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
+ MI->getOperand(3).isImm() && "Invalid insert_subreg");
+
+ unsigned DstReg = MI->getOperand(0).getReg();
+#ifndef NDEBUG
+ unsigned SrcReg = MI->getOperand(1).getReg();
+#endif
+ unsigned InsReg = MI->getOperand(2).getReg();
+ unsigned SubIdx = MI->getOperand(3).getImm();
+
+ assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
+ assert(SubIdx != 0 && "Invalid index for insert_subreg");
+ unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
+ assert(DstSubReg && "invalid subregister index for register");
+ assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
+ "Insert superreg source must be in a physical register");
+ assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
+ "Inserted value must be in a physical register");
+
+ DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
+
+ if (DstSubReg == InsReg) {
+ // No need to insert an identity copy instruction. If the SrcReg was
+ // <undef>, we need to make sure it is alive by inserting a KILL
+ if (MI->getOperand(1).isUndef() && !MI->getOperand(0).isDead()) {
+ MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
+ TII->get(TargetOpcode::KILL), DstReg);
+ if (MI->getOperand(2).isUndef())
+ MIB.addReg(InsReg, RegState::Undef);
+ else
+ MIB.addReg(InsReg, RegState::Kill);
+ } else {
+ DEBUG(dbgs() << "subreg: eliminated!\n");
+ MBB->erase(MI);
+ return true;
+ }
+ } else {
+ // Insert sub-register copy
+ const TargetRegisterClass *TRC0= TRI->getPhysicalRegisterRegClass(DstSubReg);
+ const TargetRegisterClass *TRC1= TRI->getPhysicalRegisterRegClass(InsReg);
+ if (MI->getOperand(2).isUndef())
+ // If the source register being inserted is undef, then this becomes a
+ // KILL.
+ BuildMI(*MBB, MI, MI->getDebugLoc(),
+ TII->get(TargetOpcode::KILL), DstSubReg);
+ else {
+ bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1,
+ MI->getDebugLoc());
+ (void)Emitted;
+ assert(Emitted && "Subreg and Dst must be of compatible register class");
+ }
+ MachineBasicBlock::iterator CopyMI = MI;
+ --CopyMI;
+
+ // INSERT_SUBREG is a two-address instruction so it implicitly kills SrcReg.
+ if (!MI->getOperand(1).isUndef())
+ CopyMI->addOperand(MachineOperand::CreateReg(DstReg, false, true, true));
+
+ // Transfer the kill/dead flags, if needed.
+ if (MI->getOperand(0).isDead()) {
+ TransferDeadFlag(MI, DstSubReg, TRI);
+ } else {
+ // Make sure the full DstReg is live after this replacement.
+ CopyMI->addOperand(MachineOperand::CreateReg(DstReg, true, true));
+ }
+
+ // Make sure the inserted register gets killed
+ if (MI->getOperand(2).isKill() && !MI->getOperand(2).isUndef())
+ TransferKillFlag(MI, InsReg, TRI);
+ }
+
+ DEBUG({
+ MachineBasicBlock::iterator dMI = MI;
+ dbgs() << "subreg: " << *(--dMI) << "\n";
+ });
+
+ MBB->erase(MI);
+ return true;
+}
+
bool LowerSubregsInstructionPass::LowerCopy(MachineInstr *MI) {
MachineOperand &DstMO = MI->getOperand(0);
MachineOperand &SrcMO = MI->getOperand(1);
@@ -302,9 +387,10 @@
mi != me;) {
MachineBasicBlock::iterator nmi = llvm::next(mi);
MachineInstr *MI = mi;
- assert(!MI->isInsertSubreg() && "INSERT_SUBREG should no longer appear");
if (MI->isExtractSubreg()) {
MadeChange |= LowerExtract(MI);
+ } else if (MI->isInsertSubreg()) {
+ MadeChange |= LowerInsert(MI);
} else if (MI->isSubregToReg()) {
MadeChange |= LowerSubregToReg(MI);
} else if (MI->isCopy()) {
Modified: llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp?rev=107744&r1=107743&r2=107744&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp Tue Jul 6 19:32:25 2010
@@ -102,6 +102,21 @@
continue;
}
+ if (MI->isInsertSubreg()) {
+ MachineOperand &MO = MI->getOperand(2);
+ if (ImpDefRegs.count(MO.getReg())) {
+ // %reg1032<def> = INSERT_SUBREG %reg1032, undef, 2
+ // This is an identity copy, eliminate it now.
+ if (MO.isKill()) {
+ LiveVariables::VarInfo& vi = lv_->getVarInfo(MO.getReg());
+ vi.removeKill(MI);
+ }
+ MI->eraseFromParent();
+ Changed = true;
+ continue;
+ }
+ }
+
// Eliminate %reg1032:sub<def> = COPY undef.
if (MI->isCopy() && MI->getOperand(0).getSubReg()) {
MachineOperand &MO = MI->getOperand(1);
Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=107744&r1=107743&r2=107744&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Tue Jul 6 19:32:25 2010
@@ -54,7 +54,7 @@
DstSub = MI->getOperand(0).getSubReg();
Src = MI->getOperand(1).getReg();
SrcSub = compose(MI->getOperand(1).getSubReg(), MI->getOperand(2).getImm());
- } else if (MI->isSubregToReg()) {
+ } else if (MI->isInsertSubreg() || MI->isSubregToReg()) {
Dst = MI->getOperand(0).getReg();
DstSub = compose(MI->getOperand(0).getSubReg(), MI->getOperand(3).getImm());
Src = MI->getOperand(2).getReg();
Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=107744&r1=107743&r2=107744&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Tue Jul 6 19:32:25 2010
@@ -1523,7 +1523,12 @@
if (Inst->isCopy() || Inst->isExtractSubreg()) {
DstReg = Inst->getOperand(0).getReg();
SrcReg = Inst->getOperand(1).getReg();
- } else if (Inst->isSubregToReg()) {
+ } else if (Inst->isInsertSubreg()) {
+ DstReg = Inst->getOperand(0).getReg();
+ SrcReg = Inst->getOperand(2).getReg();
+ if (Inst->getOperand(1).isUndef())
+ isInsUndef = true;
+ } else if (Inst->isInsertSubreg() || Inst->isSubregToReg()) {
DstReg = Inst->getOperand(0).getReg();
SrcReg = Inst->getOperand(2).getReg();
} else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
Modified: llvm/trunk/lib/CodeGen/StackSlotColoring.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackSlotColoring.cpp?rev=107744&r1=107743&r2=107744&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/StackSlotColoring.cpp (original)
+++ llvm/trunk/lib/CodeGen/StackSlotColoring.cpp Tue Jul 6 19:32:25 2010
@@ -508,7 +508,8 @@
// Abort the use is actually a sub-register def. We don't have enough
// information to figure out if it is really legal.
- if (MO.getSubReg() || MII->isExtractSubreg() || MII->isSubregToReg())
+ if (MO.getSubReg() || MII->isExtractSubreg() ||
+ MII->isInsertSubreg() || MII->isSubregToReg())
return false;
const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI);
Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=107744&r1=107743&r2=107744&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Tue Jul 6 19:32:25 2010
@@ -1359,11 +1359,25 @@
// Insert a copy or an extract to replace the original extracts.
MachineBasicBlock::iterator InsertLoc = SomeMI;
- MachineInstr *CopyMI = BuildMI(*SomeMI->getParent(), SomeMI,
- SomeMI->getDebugLoc(),
- TII->get(TargetOpcode::COPY))
- .addReg(DstReg, RegState::Define, NewDstSubIdx)
- .addReg(SrcReg, 0, NewSrcSubIdx);
+ if (NewSrcSubIdx) {
+ // Insert an extract subreg.
+ BuildMI(*SomeMI->getParent(), InsertLoc, SomeMI->getDebugLoc(),
+ TII->get(TargetOpcode::EXTRACT_SUBREG), DstReg)
+ .addReg(SrcReg).addImm(NewSrcSubIdx);
+ } else if (NewDstSubIdx) {
+ // Do a subreg insertion.
+ BuildMI(*SomeMI->getParent(), InsertLoc, SomeMI->getDebugLoc(),
+ TII->get(TargetOpcode::INSERT_SUBREG), DstReg)
+ .addReg(DstReg).addReg(SrcReg).addImm(NewDstSubIdx);
+ } else {
+ // Insert a copy.
+ bool Emitted =
+ TII->copyRegToReg(*SomeMI->getParent(), InsertLoc, DstReg, SrcReg,
+ MRI->getRegClass(DstReg), MRI->getRegClass(SrcReg),
+ SomeMI->getDebugLoc());
+ (void)Emitted;
+ }
+ MachineBasicBlock::iterator CopyMI = prior(InsertLoc);
// Remove all the old extract instructions.
for (MachineRegisterInfo::use_nodbg_iterator
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