[llvm-commits] [llvm] r107529 - in /llvm/trunk: include/llvm/CodeGen/MachineInstr.h include/llvm/Target/Target.td include/llvm/Target/TargetOpcodes.h lib/CodeGen/LowerSubregs.cpp utils/TableGen/CodeGenTarget.cpp
Jakob Stoklund Olesen
stoklund at 2pi.dk
Fri Jul 2 15:29:50 PDT 2010
Author: stoklund
Date: Fri Jul 2 17:29:50 2010
New Revision: 107529
URL: http://llvm.org/viewvc/llvm-project?rev=107529&view=rev
Log:
Add a new target independent COPY instruction and code to lower it.
The COPY instruction is intended to replace the target specific copy
instructions for virtual registers as well as the EXTRACT_SUBREG and
INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection
DAG.
COPY is lowered to native register copies by LowerSubregs.
Modified:
llvm/trunk/include/llvm/CodeGen/MachineInstr.h
llvm/trunk/include/llvm/Target/Target.td
llvm/trunk/include/llvm/Target/TargetOpcodes.h
llvm/trunk/lib/CodeGen/LowerSubregs.cpp
llvm/trunk/utils/TableGen/CodeGenTarget.cpp
Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=107529&r1=107528&r2=107529&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Fri Jul 2 17:29:50 2010
@@ -227,7 +227,10 @@
bool isRegSequence() const {
return getOpcode() == TargetOpcode::REG_SEQUENCE;
}
-
+ bool isCopy() const {
+ return getOpcode() == TargetOpcode::COPY;
+ }
+
/// readsRegister - Return true if the MachineInstr reads the specified
/// register. If TargetRegisterInfo is passed, then it also checks if there
/// is a read of a super-register.
Modified: llvm/trunk/include/llvm/Target/Target.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=107529&r1=107528&r2=107529&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/Target.td (original)
+++ llvm/trunk/include/llvm/Target/Target.td Fri Jul 2 17:29:50 2010
@@ -476,7 +476,6 @@
let AsmString = "DBG_VALUE";
let isAsCheapAsAMove = 1;
}
-
def REG_SEQUENCE : Instruction {
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins variable_ops);
@@ -484,6 +483,13 @@
let neverHasSideEffects = 1;
let isAsCheapAsAMove = 1;
}
+def COPY : Instruction {
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins unknown:$src);
+ let AsmString = "";
+ let neverHasSideEffects = 1;
+ let isAsCheapAsAMove = 1;
+}
}
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/include/llvm/Target/TargetOpcodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOpcodes.h?rev=107529&r1=107528&r2=107529&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetOpcodes.h (original)
+++ llvm/trunk/include/llvm/Target/TargetOpcodes.h Fri Jul 2 17:29:50 2010
@@ -75,7 +75,11 @@
/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
/// After register coalescing references of v1024 should be replace with
/// v1027:3, v1025 with v1027:4, etc.
- REG_SEQUENCE = 12
+ REG_SEQUENCE = 12,
+
+ /// COPY - Target-independent register copy. This instruction can also be
+ /// used to copy between subregisters of virtual registers.
+ COPY = 13
};
} // end namespace TargetOpcode
} // end namespace llvm
Modified: llvm/trunk/lib/CodeGen/LowerSubregs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LowerSubregs.cpp?rev=107529&r1=107528&r2=107529&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LowerSubregs.cpp (original)
+++ llvm/trunk/lib/CodeGen/LowerSubregs.cpp Fri Jul 2 17:29:50 2010
@@ -56,6 +56,7 @@
bool LowerExtract(MachineInstr *MI);
bool LowerInsert(MachineInstr *MI);
bool LowerSubregToReg(MachineInstr *MI);
+ bool LowerCopy(MachineInstr *MI);
void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
const TargetRegisterInfo *TRI);
@@ -321,6 +322,52 @@
return true;
}
+bool LowerSubregsInstructionPass::LowerCopy(MachineInstr *MI) {
+ MachineOperand &DstMO = MI->getOperand(0);
+ MachineOperand &SrcMO = MI->getOperand(1);
+
+ if (SrcMO.getReg() == DstMO.getReg()) {
+ DEBUG(dbgs() << "identity copy: " << *MI);
+ // No need to insert an identity copy instruction, but replace with a KILL
+ // if liveness is changed.
+ if (DstMO.isDead() || SrcMO.isUndef() || MI->getNumOperands() > 2) {
+ // We must make sure the super-register gets killed. Replace the
+ // instruction with KILL.
+ MI->setDesc(TII->get(TargetOpcode::KILL));
+ DEBUG(dbgs() << "replaced by: " << *MI);
+ return true;
+ }
+ // Vanilla identity copy.
+ MI->eraseFromParent();
+ return true;
+ }
+
+ DEBUG(dbgs() << "real copy: " << *MI);
+ // Ask target for a lowered copy instruction.
+ const TargetRegisterClass *DstRC =
+ TRI->getPhysicalRegisterRegClass(DstMO.getReg());
+ const TargetRegisterClass *SrcRC =
+ TRI->getPhysicalRegisterRegClass(SrcMO.getReg());
+ bool Emitted = TII->copyRegToReg(*MI->getParent(), MI,
+ DstMO.getReg(), SrcMO.getReg(),
+ DstRC, SrcRC, MI->getDebugLoc());
+ (void)Emitted;
+ assert(Emitted && "Cannot emit copy");
+
+ if (DstMO.isDead())
+ TransferDeadFlag(MI, DstMO.getReg(), TRI);
+ if (SrcMO.isKill())
+ TransferKillFlag(MI, SrcMO.getReg(), TRI, true);
+ if (MI->getNumOperands() > 2)
+ TransferImplicitDefs(MI);
+ DEBUG({
+ MachineBasicBlock::iterator dMI = MI;
+ dbgs() << "replaced by: " << *(--dMI);
+ });
+ MI->eraseFromParent();
+ return true;
+}
+
/// runOnMachineFunction - Reduce subregister inserts and extracts to register
/// copies.
///
@@ -346,6 +393,8 @@
MadeChange |= LowerInsert(MI);
} else if (MI->isSubregToReg()) {
MadeChange |= LowerSubregToReg(MI);
+ } else if (MI->isCopy()) {
+ MadeChange |= LowerCopy(MI);
}
mi = nmi;
}
Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=107529&r1=107528&r2=107529&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Fri Jul 2 17:29:50 2010
@@ -344,6 +344,7 @@
"COPY_TO_REGCLASS",
"DBG_VALUE",
"REG_SEQUENCE",
+ "COPY",
0
};
const DenseMap<const Record*, CodeGenInstruction*> &Insts = getInstructions();
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