[llvm-commits] [llvm] r107189 - in /llvm/trunk: lib/CodeGen/LowerSubregs.cpp test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll

[Bob Wilson]

Author: bwilson
Date: Tue Jun 29 13:42:49 2010
New Revision: 107189

URL: http://llvm.org/viewvc/llvm-project?rev=107189&view=rev
Log:
Fix a register scavenger crash when dealing with undefined subregs.
The LowerSubregs pass needs to preserve implicit def operands attached to
EXTRACT_SUBREG instructions when it replaces those instructions with copies.

Added:
    llvm/trunk/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll
Modified:
    llvm/trunk/lib/CodeGen/LowerSubregs.cpp

Modified: llvm/trunk/lib/CodeGen/LowerSubregs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LowerSubregs.cpp?rev=107189&r1=107188&r2=107189&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LowerSubregs.cpp (original)
+++ llvm/trunk/lib/CodeGen/LowerSubregs.cpp Tue Jun 29 13:42:49 2010
@@ -62,6 +62,7 @@
     void TransferKillFlag(MachineInstr *MI, unsigned SrcReg,
                           const TargetRegisterInfo *TRI,
                           bool AddIfNotFound = false);
+    void TransferImplicitDefs(MachineInstr *MI);
   };
 
   char LowerSubregsInstructionPass::ID = 0;
@@ -104,6 +105,22 @@
   }
 }
 
+/// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered
+/// replacement instructions immediately precede it.  Copy any implicit-def
+/// operands from MI to the replacement instruction.
+void
+LowerSubregsInstructionPass::TransferImplicitDefs(MachineInstr *MI) {
+  MachineBasicBlock::iterator CopyMI = MI;
+  --CopyMI;
+
+  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+    MachineOperand &MO = MI->getOperand(i);
+    if (!MO.isReg() || !MO.isImplicit() || MO.isUse())
+      continue;
+    CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true));
+  }
+}
+
 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
   MachineBasicBlock *MBB = MI->getParent();
 
@@ -149,6 +166,7 @@
       TransferDeadFlag(MI, DstReg, TRI);
     if (MI->getOperand(1).isKill())
       TransferKillFlag(MI, SuperReg, TRI, true);
+    TransferImplicitDefs(MI);
     DEBUG({
         MachineBasicBlock::iterator dMI = MI;
         dbgs() << "subreg: " << *(--dMI);

Added: llvm/trunk/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll?rev=107189&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll Tue Jun 29 13:42:49 2010
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=arm -mattr=+neon
+
+ at .str271 = external constant [21 x i8], align 4   ; <[21 x i8]*> [#uses=1]
+ at llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (i32, i8**)* @main to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define i32 @main(i32 %argc, i8** %argv) nounwind {
+entry:
+  %0 = shufflevector <2 x i64> undef, <2 x i64> zeroinitializer, <2 x i32> <i32 1, i32 2> ; <<2 x i64>> [#uses=1]
+  store <2 x i64> %0, <2 x i64>* undef, align 16
+  %val4723 = load <8 x i16>* undef                ; <<8 x i16>> [#uses=1]
+  call void @PrintShortX(i8* getelementptr inbounds ([21 x i8]* @.str271, i32 0, i32 0), <8 x i16> %val4723, i32 0) nounwind
+  ret i32 undef
+}
+
+declare void @PrintShortX(i8*, <8 x i16>, i32) nounwind