[llvm-commits] [llvm] r106693 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h test/CodeGen/ARM/lsr-on-unrolled-loops.ll

[Jim Grosbach]

On Jun 23, 2010, at 4:46 PM, Dale Johannesen wrote:

> 
> On Jun 23, 2010, at 4:00 PMPDT, Bill Wendling wrote:
> 
>> Author: void
>> Date: Wed Jun 23 18:00:16 2010
>> New Revision: 106693
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=106693&view=rev
>> Log:
>> We are missing opportunites to use ldm. Take code like this:
>> 
>> void t(int *cp0, int *cp1, int *dp, int fmd) {
>> int c0, c1, d0, d1, d2, d3;
>> c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
>> c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
>> /* ... */
>> }
> 
> You can't combine volatile loads, is there a check for this?
> 
> I'm also wondering if interference could be a problem, where one  
> pointer points to the other one.  I think it's OK as long as there are  
> no stores, as in the example. 
> 

You're right, those are potential gotchas. The ARMLoadStoreOptimizer pass checks for both of those conditions. Bill's patch is adjusting the DAG scheduler to help it keep related loads closer together so that the actual optimization pass will see them and be able to combine them effectively.



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