[llvm-commits] [llvm] r106333 - in /llvm/trunk: lib/CodeGen/LiveIntervalAnalysis.cpp test/CodeGen/Thumb2/crash.ll

[Evan Cheng]

On Jun 18, 2010, at 3:29 PM, Jakob Stoklund Olesen wrote:

> Author: stoklund
> Date: Fri Jun 18 17:29:44 2010
> New Revision: 106333
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=106333&view=rev
> Log:
> TwoAddressInstructionPass::CoalesceExtSubRegs can insert INSERT_SUBREG
> instructions, but it doesn't really understand live ranges, so the first
> INSERT_SUBREG uses an implicitly defined register.
> 
> Fix it in LiveVariableAnalysis by adding the <undef> flag.

Is this correct? Two-address pass is run even when livevariableanalysis is not.

Evan

> 
> Modified:
>    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
>    llvm/trunk/test/CodeGen/Thumb2/crash.ll
> 
> Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=106333&r1=106332&r2=106333&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
> +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Fri Jun 18 17:29:44 2010
> @@ -329,9 +329,16 @@
>     MachineInstr *CopyMI = NULL;
>     unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
>     if (mi->isExtractSubreg() || mi->isInsertSubreg() || mi->isSubregToReg() ||
> -        tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg))
> +        tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
>       CopyMI = mi;
> 
> +      // Some of the REG_SEQUENCE lowering in TwoAddressInstrPass creates
> +      // implicit defs without really knowing. It shows up as INSERT_SUBREG
> +      // using an undefined register.
> +      if (mi->isInsertSubreg())
> +        mi->getOperand(1).setIsUndef();
> +    }
> +
>     VNInfo *ValNo = interval.getNextValue(defIndex, CopyMI, true,
>                                           VNInfoAllocator);
>     assert(ValNo->id == 0 && "First value in interval is not 0?");
> 
> Modified: llvm/trunk/test/CodeGen/Thumb2/crash.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/crash.ll?rev=106333&r1=106332&r2=106333&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Thumb2/crash.ll (original)
> +++ llvm/trunk/test/CodeGen/Thumb2/crash.ll Fri Jun 18 17:29:44 2010
> @@ -19,3 +19,31 @@
> }
> 
> declare void @llvm.arm.neon.vst4.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>) nounwind
> +
> + at sbuf = common global [16 x i32] zeroinitializer, align 16 ; <[16 x i32]*> [#uses=5]
> + at dbuf = common global [16 x i32] zeroinitializer  ; <[16 x i32]*> [#uses=2]
> +
> +; This function creates 4 chained INSERT_SUBREGS and then invokes the register scavenger.
> +; The first INSERT_SUBREG needs an <undef> use operand for that to work.
> +define arm_apcscc i32 @main() nounwind {
> +bb.nph:
> +  br label %bb
> +
> +bb:                                               ; preds = %bb, %bb.nph
> +  %0 = phi i32 [ 0, %bb.nph ], [ %1, %bb ]        ; <i32> [#uses=4]
> +  %scevgep = getelementptr [16 x i32]* @sbuf, i32 0, i32 %0 ; <i32*> [#uses=1]
> +  %scevgep5 = getelementptr [16 x i32]* @dbuf, i32 0, i32 %0 ; <i32*> [#uses=1]
> +  store i32 %0, i32* %scevgep, align 4
> +  store i32 -1, i32* %scevgep5, align 4
> +  %1 = add nsw i32 %0, 1                          ; <i32> [#uses=2]
> +  %exitcond = icmp eq i32 %1, 16                  ; <i1> [#uses=1]
> +  br i1 %exitcond, label %bb2, label %bb
> +
> +bb2:                                              ; preds = %bb
> +  %2 = load <4 x i32>* bitcast ([16 x i32]* @sbuf to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1]
> +  %3 = load <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32]* @sbuf, i32 0, i32 4) to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1]
> +  %4 = load <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32]* @sbuf, i32 0, i32 8) to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1]
> +  %5 = load <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32]* @sbuf, i32 0, i32 12) to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1]
> +  tail call void @llvm.arm.neon.vst4.v4i32(i8* bitcast ([16 x i32]* @dbuf to i8*), <4 x i32> %2, <4 x i32> %3, <4 x i32> %4, <4 x i32> %5) nounwind
> +  ret i32 0
> +}
> 
> 
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