[llvm-commits] [llvm] r106327 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td

[Bruno Cardoso Lopes]

Author: bruno
Date: Fri Jun 18 17:10:11 2010
New Revision: 106327

URL: http://llvm.org/viewvc/llvm-project?rev=106327&view=rev
Log:
Use the new 'defm' class inheritance in SSE

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=106327&r1=106326&r2=106327&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Jun 18 17:10:11 2010
@@ -672,29 +672,25 @@
 multiclass basic_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
                                  SDNode OpNode, bit Commutable = 0> {
 
-  let Constraints = "", isAsmParserOnly = 1, hasVEX_4VPrefix = 1 in {
+  let Constraints = "", isAsmParserOnly = 1 in {
     // Scalar operation, reg+reg.
-    let Prefix = 12 /* XS */ in
-      defm V#NAME#SS : sse12_fp_scalar<opc,
+    defm V#NAME#SS : sse12_fp_scalar<opc,
         !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-                   OpNode, FR32, f32mem>;
+                   OpNode, FR32, f32mem>, XS, VEX_4V;
 
-    let Prefix = 11 /* XD */ in
-      defm V#NAME#SD : sse12_fp_scalar<opc,
+    defm V#NAME#SD : sse12_fp_scalar<opc,
         !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-                   OpNode, FR64, f64mem>;
+                   OpNode, FR64, f64mem>, XD, VEX_4V;
   }
 
   let Constraints = "$src1 = $dst" in {
     // Scalar operation, reg+reg.
-    let Prefix = 12 /* XS */ in
-      defm SS : sse12_fp_scalar<opc,
-                      !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
-                      OpNode, FR32, f32mem>;
-    let Prefix = 11 /* XD */ in
-      defm SD : sse12_fp_scalar<opc,
-                      !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
-                      OpNode, FR64, f64mem>;
+    defm SS : sse12_fp_scalar<opc,
+                    !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
+                    OpNode, FR32, f32mem>, XS;
+    defm SD : sse12_fp_scalar<opc,
+                    !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
+                    OpNode, FR64, f64mem>, XD;
   }
 
   // Vector operation, reg+reg.
@@ -857,29 +853,25 @@
 multiclass sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
                             SDNode OpNode, bit Commutable = 0> {
 
-  let Constraints = "", isAsmParserOnly = 1, hasVEX_4VPrefix = 1 in {
+  let Constraints = "", isAsmParserOnly = 1 in {
     // Scalar operation, reg+reg.
-    let Prefix = 12 /* XS */ in
-      defm V#NAME#SS : sse12_fp_scalar<opc,
-        !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-                   OpNode, FR32, f32mem>;
-
-    let Prefix = 11 /* XD */ in
-      defm V#NAME#SD : sse12_fp_scalar<opc,
-        !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-                   OpNode, FR64, f64mem>;
+    defm V#NAME#SS : sse12_fp_scalar<opc,
+      !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+                 OpNode, FR32, f32mem>, XS, VEX_4V;
+
+    defm V#NAME#SD : sse12_fp_scalar<opc,
+      !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+                 OpNode, FR64, f64mem>, XD, VEX_4V;
   }
 
   let Constraints = "$src1 = $dst" in {
     // Scalar operation, reg+reg.
-    let Prefix = 12 /* XS */ in
-      defm SS : sse12_fp_scalar<opc,
-                      !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
-                      OpNode, FR32, f32mem>;
-    let Prefix = 11 /* XD */ in
-      defm SD : sse12_fp_scalar<opc,
-                      !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
-                      OpNode, FR64, f64mem>;
+    defm SS : sse12_fp_scalar<opc,
+                    !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
+                    OpNode, FR32, f32mem>, XS;
+    defm SD : sse12_fp_scalar<opc,
+                    !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
+                    OpNode, FR64, f64mem>, XD;
   }
 
   // Vector operation, reg+reg.