[llvm-commits] [llvm] r105308 - in /llvm/trunk: lib/CodeGen/MachineCSE.cpp test/CodeGen/ARM/machine-cse-cmp.ll

[Evan Cheng]

Author: evancheng
Date: Tue Jun  1 20:08:27 2010
New Revision: 105308

URL: http://llvm.org/viewvc/llvm-project?rev=105308&view=rev
Log:
Enable machine cse of instructions which define physical registers.

Added:
    llvm/trunk/test/CodeGen/ARM/machine-cse-cmp.ll
Modified:
    llvm/trunk/lib/CodeGen/MachineCSE.cpp

Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCSE.cpp?rev=105308&r1=105307&r2=105308&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineCSE.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineCSE.cpp Tue Jun  1 20:08:27 2010
@@ -31,9 +31,6 @@
 STATISTIC(NumCoalesces, "Number of copies coalesced");
 STATISTIC(NumCSEs,      "Number of common subexpression eliminated");
 
-static cl::opt<bool> CSEPhysDef("machine-cse-phys-defs",
-                                cl::init(false), cl::Hidden);
-
 namespace {
   class MachineCSE : public MachineFunctionPass {
     const TargetInstrInfo *TII;
@@ -376,7 +373,7 @@
 
       // ... Unless the CS is local and it also defines the physical register
       // which is not clobbered in between.
-      if (PhysDef && CSEPhysDef) {
+      if (PhysDef) {
         unsigned CSVN = VNT.lookup(MI);
         MachineInstr *CSMI = Exps[CSVN];
         if (PhysRegDefReaches(CSMI, MI, PhysDef))

Added: llvm/trunk/test/CodeGen/ARM/machine-cse-cmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/machine-cse-cmp.ll?rev=105308&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/machine-cse-cmp.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/machine-cse-cmp.ll Tue Jun  1 20:08:27 2010
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=arm | FileCheck %s
+;rdar://8003725
+
+ at G1 = external global i32
+ at G2 = external global i32
+
+define i32 @f1(i32 %cond1, i32 %x1, i32 %x2, i32 %x3) {
+entry:
+; CHECK: cmp
+; CHECK: moveq
+; CHECK-NOT: cmp
+; CHECK: moveq
+    %tmp1 = icmp eq i32 %cond1, 0
+    %tmp2 = select i1 %tmp1, i32 %x1, i32 %x2
+    %tmp3 = select i1 %tmp1, i32 %x2, i32 %x3
+    %tmp4 = add i32 %tmp2, %tmp3
+    ret i32 %tmp4
+}