[llvm-commits] [llvm] r105283 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeTypes.h lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/X86/vector-intrinsics.ll
Dan Gohman
gohman at apple.com
Tue Jun 1 11:35:14 PDT 2010
Author: djg
Date: Tue Jun 1 13:35:14 2010
New Revision: 105283
URL: http://llvm.org/viewvc/llvm-project?rev=105283&view=rev
Log:
Fill in missing support for ISD::FEXP, ISD::FPOWI, and friends.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/trunk/test/CodeGen/X86/vector-intrinsics.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=105283&r1=105282&r2=105283&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Tue Jun 1 13:35:14 2010
@@ -620,6 +620,7 @@
SDValue WidenVecRes_Binary(SDNode *N);
SDValue WidenVecRes_Convert(SDNode *N);
+ SDValue WidenVecRes_POWI(SDNode *N);
SDValue WidenVecRes_Shift(SDNode *N);
SDValue WidenVecRes_Unary(SDNode *N);
SDValue WidenVecRes_InregOp(SDNode *N);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=105283&r1=105282&r2=105283&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Jun 1 13:35:14 2010
@@ -448,6 +448,11 @@
case ISD::SIGN_EXTEND:
case ISD::ZERO_EXTEND:
case ISD::ANY_EXTEND:
+ case ISD::FEXP:
+ case ISD::FEXP2:
+ case ISD::FLOG:
+ case ISD::FLOG2:
+ case ISD::FLOG10:
SplitVecRes_UnaryOp(N, Lo, Hi);
break;
@@ -1199,7 +1204,6 @@
case ISD::FDIV:
case ISD::FMUL:
case ISD::FPOW:
- case ISD::FPOWI:
case ISD::FREM:
case ISD::FSUB:
case ISD::MUL:
@@ -1215,6 +1219,10 @@
Res = WidenVecRes_Binary(N);
break;
+ case ISD::FPOWI:
+ Res = WidenVecRes_POWI(N);
+ break;
+
case ISD::SHL:
case ISD::SRA:
case ISD::SRL:
@@ -1241,6 +1249,11 @@
case ISD::FNEG:
case ISD::FSIN:
case ISD::FSQRT:
+ case ISD::FEXP:
+ case ISD::FEXP2:
+ case ISD::FLOG:
+ case ISD::FLOG2:
+ case ISD::FLOG10:
Res = WidenVecRes_Unary(N);
break;
}
@@ -1410,6 +1423,13 @@
return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
}
+SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+ SDValue InOp = GetWidenedVector(N->getOperand(0));
+ SDValue ShOp = N->getOperand(1);
+ return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
+}
+
SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
SDValue InOp = GetWidenedVector(N->getOperand(0));
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=105283&r1=105282&r2=105283&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Jun 1 13:35:14 2010
@@ -5674,13 +5674,16 @@
case ISD::FSQRT: return "fsqrt";
case ISD::FSIN: return "fsin";
case ISD::FCOS: return "fcos";
- case ISD::FPOWI: return "fpowi";
- case ISD::FPOW: return "fpow";
case ISD::FTRUNC: return "ftrunc";
case ISD::FFLOOR: return "ffloor";
case ISD::FCEIL: return "fceil";
case ISD::FRINT: return "frint";
case ISD::FNEARBYINT: return "fnearbyint";
+ case ISD::FEXP: return "fexp";
+ case ISD::FEXP2: return "fexp2";
+ case ISD::FLOG: return "flog";
+ case ISD::FLOG2: return "flog2";
+ case ISD::FLOG10: return "flog10";
// Binary operators
case ISD::ADD: return "add";
@@ -5711,7 +5714,9 @@
case ISD::FREM: return "frem";
case ISD::FCOPYSIGN: return "fcopysign";
case ISD::FGETSIGN: return "fgetsign";
+ case ISD::FPOW: return "fpow";
+ case ISD::FPOWI: return "fpowi";
case ISD::SETCC: return "setcc";
case ISD::VSETCC: return "vsetcc";
case ISD::SELECT: return "select";
Modified: llvm/trunk/test/CodeGen/X86/vector-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-intrinsics.ll?rev=105283&r1=105282&r2=105283&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vector-intrinsics.ll Tue Jun 1 13:35:14 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 | grep call | count 16
+; RUN: llc < %s -march=x86-64 | grep call | count 43
declare <4 x double> @llvm.sin.v4f64(<4 x double> %p)
declare <4 x double> @llvm.cos.v4f64(<4 x double> %p)
@@ -25,3 +25,28 @@
%t = call <4 x double> @llvm.powi.v4f64(<4 x double> %p, i32 %q)
ret <4 x double> %t
}
+
+
+declare <9 x double> @llvm.exp.v9f64(<9 x double> %a)
+declare <9 x double> @llvm.pow.v9f64(<9 x double> %a, <9 x double> %b)
+declare <9 x double> @llvm.powi.v9f64(<9 x double> %a, i32)
+
+define void @a(<9 x double>* %p) nounwind {
+ %a = load <9 x double>* %p
+ %r = call <9 x double> @llvm.exp.v9f64(<9 x double> %a)
+ store <9 x double> %r, <9 x double>* %p
+ ret void
+}
+define void @b(<9 x double>* %p, <9 x double>* %q) nounwind {
+ %a = load <9 x double>* %p
+ %b = load <9 x double>* %q
+ %r = call <9 x double> @llvm.pow.v9f64(<9 x double> %a, <9 x double> %b)
+ store <9 x double> %r, <9 x double>* %p
+ ret void
+}
+define void @c(<9 x double>* %p, i32 %n) nounwind {
+ %a = load <9 x double>* %p
+ %r = call <9 x double> @llvm.powi.v9f64(<9 x double> %a, i32 %n)
+ store <9 x double> %r, <9 x double>* %p
+ ret void
+}
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