[llvm-commits] [llvm] r104883 - /llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp

[Bob Wilson]

Author: bwilson
Date: Thu May 27 15:23:42 2010
New Revision: 104883

URL: http://llvm.org/viewvc/llvm-project?rev=104883&view=rev
Log:
Fix some bad fall-throughs in a switch statement.  Both the 'Q' and 'R' cases
should fall through to the 'H' case, but instead 'Q' was falling through to 'R'
so that it would do the wrong thing for a big-endian ARM target.

Modified:
    llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=104883&r1=104882&r2=104883&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Thu May 27 15:23:42 2010
@@ -1064,21 +1064,27 @@
       printOperand(MI, OpNum, O);
       return false;
     case 'Q':
-      if (TM.getTargetData()->isLittleEndian())
+      // Print the least significant half of a register pair.
+      if (TM.getTargetData()->isBigEndian())
         break;
-      // Fallthrough
+      printOperand(MI, OpNum, O);
+      return false;
     case 'R':
-      if (TM.getTargetData()->isBigEndian())
+      // Print the most significant half of a register pair.
+      if (TM.getTargetData()->isLittleEndian())
         break;
-      // Fallthrough
-    case 'H': // Write second word of DI / DF reference.
-      // Verify that this operand has two consecutive registers.
-      if (!MI->getOperand(OpNum).isReg() ||
-          OpNum+1 == MI->getNumOperands() ||
-          !MI->getOperand(OpNum+1).isReg())
-        return true;
-      ++OpNum;   // Return the high-part.
+      printOperand(MI, OpNum, O);
+      return false;
+    case 'H':
+      break;
     }
+    // Print the second half of a register pair (for 'Q', 'R' or 'H').
+    // Verify that this operand has two consecutive registers.
+    if (!MI->getOperand(OpNum).isReg() ||
+        OpNum+1 == MI->getNumOperands() ||
+        !MI->getOperand(OpNum+1).isReg())
+      return true;
+    ++OpNum;
   }
 
   printOperand(MI, OpNum, O);