[llvm-commits] [llvm] r104704 - in /llvm/trunk: include/llvm/Target/Target.td lib/Target/ARM/ARMRegisterInfo.td lib/Target/Blackfin/BlackfinRegisterInfo.td lib/Target/MBlaze/MBlazeRegisterInfo.td lib/Target/MSP430/MSP430RegisterInfo.td lib/Target

[Jakob Stoklund Olesen]

On May 26, 2010, at 11:05 AM, Anton Korobeynikov wrote:

>> Is it wrong that we have ssub_0 to ssub_3? It sounds like ssub_2 and ssub_3 are not legal?
> Well, this is pretty good question :) For some operations we need to
> restrict to some part of register file (all that _VFP2 / _8
> regclasses). And thus we have to model the whole hierarchy of subregs.

At least, it is a lot easier now :-)

The coalescer needs to be able to compose subreg indices. Suppose an instruction uses parts of a DPR_VFP2 register:

FOO %reg1100:ssub_1

And now %reg1100 is coalesced with the second part of a Q register:

%reg1100 = COPY %reg1200:dsub_1

The FOO instruction must be updated to: FOO %reg1200:dsub_1:ssub_1

Which is really: FOO %reg1200:ssub_3

We need a target hook to compose ssub_3 = dsub_1 + ssub_1, and I need to require names for all inherited subregisters to implement that.

Right now, the ARM register bank is not fully named:

Warning: Register QQ0 inherited subregisters without an index:
  S4 = qsub_1, ssub_0
  S5 = qsub_1, ssub_1
  S6 = qsub_1, ssub_2
  S7 = qsub_1, ssub_3
Warning: Register QQQQ0 inherited subregisters without an index:
  S10 = qqsub_1, ssub_2
  S11 = qqsub_1, ssub_3
  S8 = qqsub_1, ssub_0
  S9 = qqsub_1, ssub_1

So I am probably going to add ssub_4 through ssub_15.