[llvm-commits] [llvm] r104660 - in /llvm/trunk: include/llvm/Target/Target.td lib/Target/ARM/ARMRegisterInfo.td lib/Target/Blackfin/BlackfinRegisterInfo.td lib/Target/MBlaze/MBlazeRegisterInfo.td lib/Target/MSP430/MSP430RegisterInfo.td lib/Target/Mips/MipsRegisterInfo.td lib/Target/PowerPC/PPCRegisterInfo.td lib/Target/Sparc/SparcRegisterInfo.td lib/Target/SystemZ/SystemZRegisterInfo.td lib/Target/X86/X86RegisterInfo.td utils/TableGen/RegisterInfoEmitter.cpp
Jakob Stoklund Olesen
stoklund at 2pi.dk
Tue May 25 18:21:14 PDT 2010
Author: stoklund
Date: Tue May 25 20:21:14 2010
New Revision: 104660
URL: http://llvm.org/viewvc/llvm-project?rev=104660&view=rev
Log:
Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."
This reverts commit 104654.
Modified:
llvm/trunk/include/llvm/Target/Target.td
llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td
llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.td
llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.td
llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td
llvm/trunk/lib/Target/X86/X86RegisterInfo.td
llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
Modified: llvm/trunk/include/llvm/Target/Target.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=104660&r1=104659&r2=104660&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/Target.td (original)
+++ llvm/trunk/include/llvm/Target/Target.td Tue May 25 20:21:14 2010
@@ -54,23 +54,6 @@
// not [AX, AH, AL].
list<Register> SubRegs = [];
- // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
- // to address it. Sub-sub-register indices are automatically inherited from
- // SubRegs.
- list<SubRegIndex> SubRegIndices = [];
-
- // CompositeIndices - Specify subreg indices that don't correspond directly to
- // a register in SubRegs and are not inherited. The following formats are
- // supported:
- //
- // (a) Identity - Reg:a == Reg
- // (a b) Alias - Reg:a == Reg:b
- // (a b,c) Composite - Reg:a == (Reg:b):c
- //
- // This can be used to disambiguate a sub-sub-register that exists in more
- // than one subregister and other weird stuff.
- list<dag> CompositeIndices = [];
-
// DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
// These values can be determined by locating the <target>.h file in the
// directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
@@ -90,6 +73,17 @@
let SubRegs = subregs;
}
+// SubRegSet - This can be used to define a specific mapping of registers to
+// indices, for use as named subregs of a particular physical register. Each
+// register in 'subregs' becomes an addressable subregister at index 'n' of the
+// corresponding register in 'regs'.
+class SubRegSet<SubRegIndex n, list<Register> regs, list<Register> subregs> {
+ SubRegIndex Index = n;
+
+ list<Register> From = regs;
+ list<Register> To = subregs;
+}
+
// RegisterClass - Now that all of the registers are defined, and aliases
// between registers are defined, specify which registers belong to which
// register classes. This also defines the default allocation order of
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=104660&r1=104659&r2=104660&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Tue May 25 20:21:14 2010
@@ -86,7 +86,6 @@
def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">;
// Aliases of the F* registers used to hold 64-bit fp values (doubles)
-let SubRegIndices = [ssub_0, ssub_1] in {
def D0 : ARMReg< 0, "d0", [S0, S1]>;
def D1 : ARMReg< 1, "d1", [S2, S3]>;
def D2 : ARMReg< 2, "d2", [S4, S5]>;
@@ -103,7 +102,6 @@
def D13 : ARMReg<13, "d13", [S26, S27]>;
def D14 : ARMReg<14, "d14", [S28, S29]>;
def D15 : ARMReg<15, "d15", [S30, S31]>;
-}
// VFP3 defines 16 additional double registers
def D16 : ARMFReg<16, "d16">; def D17 : ARMFReg<17, "d17">;
@@ -116,9 +114,6 @@
def D30 : ARMFReg<30, "d30">; def D31 : ARMFReg<31, "d31">;
// Advanced SIMD (NEON) defines 16 quad-word aliases
-let SubRegIndices = [dsub_0, dsub_1],
- CompositeIndices = [(ssub_2 dsub_1, ssub_0),
- (ssub_3 dsub_1, ssub_1)] in {
def Q0 : ARMReg< 0, "q0", [D0, D1]>;
def Q1 : ARMReg< 1, "q1", [D2, D3]>;
def Q2 : ARMReg< 2, "q2", [D4, D5]>;
@@ -127,8 +122,6 @@
def Q5 : ARMReg< 5, "q5", [D10, D11]>;
def Q6 : ARMReg< 6, "q6", [D12, D13]>;
def Q7 : ARMReg< 7, "q7", [D14, D15]>;
-}
-let SubRegIndices = [dsub_0, dsub_1] in {
def Q8 : ARMReg< 8, "q8", [D16, D17]>;
def Q9 : ARMReg< 9, "q9", [D18, D19]>;
def Q10 : ARMReg<10, "q10", [D20, D21]>;
@@ -137,7 +130,6 @@
def Q13 : ARMReg<13, "q13", [D26, D27]>;
def Q14 : ARMReg<14, "q14", [D28, D29]>;
def Q15 : ARMReg<15, "q15", [D30, D31]>;
-}
// Pseudo 256-bit registers to represent pairs of Q registers. These should
// never be present in the emitted code.
@@ -146,9 +138,6 @@
// starting D register number doesn't have to be multiple of 4. e.g.
// D1, D2, D3, D4 would be a legal quad. But that would make the sub-register
// stuffs very messy.
-let SubRegIndices = [qsub_0, qsub_1],
- CompositeIndices = [(dsub_2 qsub_1, dsub_0),
- (dsub_3 qsub_1, dsub_1)] in {
def QQ0 : ARMReg<0, "qq0", [Q0, Q1]>;
def QQ1 : ARMReg<1, "qq1", [Q2, Q3]>;
def QQ2 : ARMReg<2, "qq2", [Q4, Q5]>;
@@ -157,21 +146,12 @@
def QQ5 : ARMReg<5, "qq5", [Q10, Q11]>;
def QQ6 : ARMReg<6, "qq6", [Q12, Q13]>;
def QQ7 : ARMReg<7, "qq7", [Q14, Q15]>;
-}
// Pseudo 512-bit registers to represent four consecutive Q registers.
-let SubRegIndices = [qqsub_0, qqsub_1],
- CompositeIndices = [(qsub_2 qqsub_1, qsub_0),
- (qsub_3 qqsub_1, qsub_1),
- (dsub_4 qqsub_1, dsub_0),
- (dsub_5 qqsub_1, dsub_1),
- (dsub_6 qqsub_1, dsub_2),
- (dsub_7 qqsub_1, dsub_3)] in {
def QQQQ0 : ARMReg<0, "qqqq0", [QQ0, QQ1]>;
def QQQQ1 : ARMReg<1, "qqqq1", [QQ2, QQ3]>;
def QQQQ2 : ARMReg<2, "qqqq2", [QQ4, QQ5]>;
def QQQQ3 : ARMReg<3, "qqqq3", [QQ6, QQ7]>;
-}
// Current Program Status Register.
def CPSR : ARMReg<0, "cpsr">;
@@ -458,3 +438,102 @@
// Condition code registers.
def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;
+//===----------------------------------------------------------------------===//
+// Subregister Set Definitions... now that we have all of the pieces, define the
+// sub registers for each register.
+//
+
+// S sub-registers of D registers.
+def : SubRegSet<ssub_0, [D0, D1, D2, D3, D4, D5, D6, D7,
+ D8, D9, D10, D11, D12, D13, D14, D15],
+ [S0, S2, S4, S6, S8, S10, S12, S14,
+ S16, S18, S20, S22, S24, S26, S28, S30]>;
+def : SubRegSet<ssub_1, [D0, D1, D2, D3, D4, D5, D6, D7,
+ D8, D9, D10, D11, D12, D13, D14, D15],
+ [S1, S3, S5, S7, S9, S11, S13, S15,
+ S17, S19, S21, S23, S25, S27, S29, S31]>;
+
+// S sub-registers of Q registers.
+def : SubRegSet<ssub_0, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
+ [S0, S4, S8, S12, S16, S20, S24, S28]>;
+def : SubRegSet<ssub_1, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
+ [S1, S5, S9, S13, S17, S21, S25, S29]>;
+def : SubRegSet<ssub_2, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
+ [S2, S6, S10, S14, S18, S22, S26, S30]>;
+def : SubRegSet<ssub_3, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
+ [S3, S7, S11, S15, S19, S23, S27, S31]>;
+
+// D sub-registers of Q registers.
+def : SubRegSet<dsub_0, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
+ Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
+ [D0, D2, D4, D6, D8, D10, D12, D14,
+ D16, D18, D20, D22, D24, D26, D28, D30]>;
+def : SubRegSet<dsub_1, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
+ Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
+ [D1, D3, D5, D7, D9, D11, D13, D15,
+ D17, D19, D21, D23, D25, D27, D29, D31]>;
+
+// S sub-registers of QQ registers. Note there are no sub-indices
+// for referencing S4 - S7, S12 - S15, and S20 - S23. It doesn't
+// look like we need them.
+def : SubRegSet<ssub_0, [QQ0, QQ1, QQ2, QQ3],
+ [S0, S8, S16, S24]>;
+def : SubRegSet<ssub_1, [QQ0, QQ1, QQ2, QQ3],
+ [S1, S9, S17, S25]>;
+def : SubRegSet<ssub_2, [QQ0, QQ1, QQ2, QQ3],
+ [S2, S10, S18, S26]>;
+def : SubRegSet<ssub_3, [QQ0, QQ1, QQ2, QQ3],
+ [S3, S11, S19, S27]>;
+
+// D sub-registers of QQ registers.
+def : SubRegSet<dsub_0, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
+ [D0, D4, D8, D12, D16, D20, D24, D28]>;
+def : SubRegSet<dsub_1, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
+ [D1, D5, D9, D13, D17, D21, D25, D29]>;
+def : SubRegSet<dsub_2, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
+ [D2, D6, D10, D14, D18, D22, D26, D30]>;
+def : SubRegSet<dsub_3, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
+ [D3, D7, D11, D15, D19, D23, D27, D31]>;
+
+// Q sub-registers of QQ registers.
+def : SubRegSet<qsub_0, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
+ [Q0, Q2, Q4, Q6, Q8, Q10, Q12, Q14]>;
+def : SubRegSet<qsub_1,[QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
+ [Q1, Q3, Q5, Q7, Q9, Q11, Q13, Q15]>;
+
+
+// D sub-registers of QQQQ registers.
+def : SubRegSet<dsub_0, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [D0, D8, D16, D24]>;
+def : SubRegSet<dsub_1, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [D1, D9, D17, D25]>;
+def : SubRegSet<dsub_2, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [D2, D10, D18, D26]>;
+def : SubRegSet<dsub_3, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [D3, D11, D19, D27]>;
+
+def : SubRegSet<dsub_4, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [D4, D12, D20, D28]>;
+def : SubRegSet<dsub_5, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [D5, D13, D21, D29]>;
+def : SubRegSet<dsub_6, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [D6, D14, D22, D30]>;
+def : SubRegSet<dsub_7, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [D7, D15, D23, D31]>;
+
+// Q sub-registers of QQQQ registers.
+def : SubRegSet<qsub_0, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [Q0, Q4, Q8, Q12]>;
+def : SubRegSet<qsub_1, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [Q1, Q5, Q9, Q13]>;
+def : SubRegSet<qsub_2, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [Q2, Q6, Q10, Q14]>;
+def : SubRegSet<qsub_3, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [Q3, Q7, Q11, Q15]>;
+
+// QQ sub-registers of QQQQ registers.
+def : SubRegSet<qqsub_0, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [QQ0, QQ2, QQ4, QQ6]>;
+def : SubRegSet<qqsub_1, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
+ [QQ1, QQ3, QQ5, QQ7]>;
+
Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td?rev=104660&r1=104659&r2=104660&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td Tue May 25 20:21:14 2010
@@ -19,7 +19,6 @@
def lo16 : SubRegIndex;
def hi16 : SubRegIndex;
def lo32 : SubRegIndex;
-def hi32 : SubRegIndex;
}
// Registers are identified with 3-bit group and 3-bit ID numbers.
@@ -50,7 +49,6 @@
// Ra 40-bit accumulator registers
class Ra<bits<3> num, string n, list<Register> subs> : BlackfinReg<n> {
let SubRegs = subs;
- let SubRegIndices = [hi32, lo32];
let Group = 4;
let Num = num;
}
@@ -65,7 +63,6 @@
class Rii<bits<3> group, bits<3> num, string n, list<Register> subs>
: BlackfinReg<n> {
let SubRegs = subs;
- let SubRegIndices = [hi16, lo16];
let Group = group;
let Num = num;
}
@@ -176,7 +173,7 @@
def RETE : Ri<7, 6, "rete">, DwarfRegNum<[39]>;
def ASTAT : Ri<4, 6, "astat">, DwarfRegNum<[40]> {
- let Aliases = [AZ, AN, CC, NCC, AQ, AC0, AC1, AV0, AV0S, AV1, AV1S, V, VS];
+ let SubRegs = [AZ, AN, CC, NCC, AQ, AC0, AC1, AV0, AV0S, AV1, AV1S, V, VS];
}
def SEQSTAT : Ri<7, 1, "seqstat">, DwarfRegNum<[41]>;
@@ -194,6 +191,29 @@
def LB0 : Ri<6, 2, "lb0">, DwarfRegNum<[48]>;
def LB1 : Ri<6, 5, "lb1">, DwarfRegNum<[49]>;
+def : SubRegSet<lo16,
+ [R0, R1, R2, R3, R4, R5, R6, R7,
+ P0, P1, P2, P3, P4, P5, SP, FP,
+ I0, I1, I2, I3, M0, M1, M2, M3,
+ B0, B1, B2, B3, L0, L1, L2, L3],
+ [R0L, R1L, R2L, R3L, R4L, R5L, R6L, R7L,
+ P0L, P1L, P2L, P3L, P4L, P5L, SPL, FPL,
+ I0L, I1L, I2L, I3L, M0L, M1L, M2L, M3L,
+ B0L, B1L, B2L, B3L, L0L, L1L, L2L, L3L]>;
+
+def : SubRegSet<hi16,
+ [R0, R1, R2, R3, R4, R5, R6, R7,
+ P0, P1, P2, P3, P4, P5, SP, FP,
+ I0, I1, I2, I3, M0, M1, M2, M3,
+ B0, B1, B2, B3, L0, L1, L2, L3],
+ [R0H, R1H, R2H, R3H, R4H, R5H, R6H, R7H,
+ P0H, P1H, P2H, P3H, P4H, P5H, SPH, FPH,
+ I0H, I1H, I2H, I3H, M0H, M1H, M2H, M3H,
+ B0H, B1H, B2H, B3H, L0H, L1H, L2H, L3H]>;
+
+def : SubRegSet<lo16, [A0, A0W, A1, A1W], [A0L, A0L, A1L, A1L]>;
+def : SubRegSet<hi16, [A0, A0W, A1, A1W], [A0H, A0H, A1H, A1H]>;
+
// Register classes.
def D16 : RegisterClass<"BF", [i16], 16,
[R0H, R0L, R1H, R1L, R2H, R2L, R3H, R3L,
Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.td?rev=104660&r1=104659&r2=104660&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.td Tue May 25 20:21:14 2010
@@ -17,15 +17,21 @@
let Namespace = "MBlaze";
}
+class MBlazeRegWithSubRegs<string n, list<Register> subregs>
+ : RegisterWithSubRegs<n, subregs> {
+ field bits<5> Num;
+ let Namespace = "MBlaze";
+}
+
// MBlaze CPU Registers
class MBlazeGPRReg<bits<5> num, string n> : MBlazeReg<n> {
let Num = num;
}
// MBlaze 32-bit (aliased) FPU Registers
-class FPR<bits<5> num, string n, list<Register> aliases> : MBlazeReg<n> {
+class FPR<bits<5> num, string n, list<Register> subregs>
+ : MBlazeRegWithSubRegs<n, subregs> {
let Num = num;
- let Aliases = aliases;
}
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td?rev=104660&r1=104659&r2=104660&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td Tue May 25 20:21:14 2010
@@ -43,9 +43,6 @@
def R14B : MSP430Reg<14, "r14">;
def R15B : MSP430Reg<15, "r15">;
-def subreg_8bit : SubRegIndex { let Namespace = "MSP430"; }
-
-let SubRegIndices = [subreg_8bit] in {
def PCW : MSP430RegWithSubregs<0, "r0", [PCB]>;
def SPW : MSP430RegWithSubregs<1, "r1", [SPB]>;
def SRW : MSP430RegWithSubregs<2, "r2", [SRB]>;
@@ -62,7 +59,13 @@
def R13W : MSP430RegWithSubregs<13, "r13", [R13B]>;
def R14W : MSP430RegWithSubregs<14, "r14", [R14B]>;
def R15W : MSP430RegWithSubregs<15, "r15", [R15B]>;
-}
+
+def subreg_8bit : SubRegIndex { let Namespace = "MSP430"; }
+
+def : SubRegSet<subreg_8bit, [PCW, SPW, SRW, CGW, FPW, R5W, R6W, R7W,
+ R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
+ [PCB, SPB, SRB, CGB, FPB, R5B, R6B, R7B,
+ R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
def GR8 : RegisterClass<"MSP430", [i8], 8,
// Volatile registers
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=104660&r1=104659&r2=104660&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Tue May 25 20:21:14 2010
@@ -34,14 +34,9 @@
}
// Mips 64-bit (aliased) FPU Registers
-let Namespace = "Mips" in {
-def sub_fpeven : SubRegIndex;
-def sub_fpodd : SubRegIndex;
-}
-class AFPR<bits<5> num, string n, list<Register> subregs>
+class AFPR<bits<5> num, string n, list<Register> subregs>
: MipsRegWithSubRegs<n, subregs> {
let Num = num;
- let SubRegIndices = [sub_fpeven, sub_fpodd];
}
//===----------------------------------------------------------------------===//
@@ -146,6 +141,25 @@
}
//===----------------------------------------------------------------------===//
+// Subregister Set Definitions
+//===----------------------------------------------------------------------===//
+
+let Namespace = "Mips" in {
+def sub_fpeven : SubRegIndex;
+def sub_fpodd : SubRegIndex;
+}
+
+def : SubRegSet<sub_fpeven, [D0, D1, D2, D3, D4, D5, D6, D7,
+ D8, D9, D10, D11, D12, D13, D14, D15],
+ [F0, F2, F4, F6, F8, F10, F12, F14,
+ F16, F18, F20, F22, F24, F26, F28, F30]>;
+
+def : SubRegSet<sub_fpodd, [D0, D1, D2, D3, D4, D5, D6, D7,
+ D8, D9, D10, D11, D12, D13, D14, D15],
+ [F1, F3, F5, F7, F9, F11, F13, F15,
+ F17, F19, F21, F23, F25, F27, F29, F31]>;
+
+//===----------------------------------------------------------------------===//
// Register Classes
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td?rev=104660&r1=104659&r2=104660&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td Tue May 25 20:21:14 2010
@@ -10,15 +10,6 @@
//
//===----------------------------------------------------------------------===//
-let Namespace = "PPC" in {
-def sub_lt : SubRegIndex;
-def sub_gt : SubRegIndex;
-def sub_eq : SubRegIndex;
-def sub_un : SubRegIndex;
-def sub_32 : SubRegIndex;
-}
-
-
class PPCReg<string n> : Register<n> {
let Namespace = "PPC";
}
@@ -34,7 +25,6 @@
class GP8<GPR SubReg, string n> : PPCReg<n> {
field bits<5> Num = SubReg.Num;
let SubRegs = [SubReg];
- let SubRegIndices = [sub_32];
}
// SPR - One of the 32-bit special-purpose registers
@@ -235,7 +225,6 @@
def CR7UN : CRBIT<31, "31">, DwarfRegNum<[0]>;
// Condition registers
-let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in {
def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68]>;
def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69]>;
def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70]>;
@@ -244,8 +233,27 @@
def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73]>;
def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74]>;
def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75]>;
+
+let Namespace = "PPC" in {
+def sub_lt : SubRegIndex;
+def sub_gt : SubRegIndex;
+def sub_eq : SubRegIndex;
+def sub_un : SubRegIndex;
}
+def : SubRegSet<sub_lt,
+ [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
+ [CR0LT, CR1LT, CR2LT, CR3LT, CR4LT, CR5LT, CR6LT, CR7LT]>;
+def : SubRegSet<sub_gt,
+ [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
+ [CR0GT, CR1GT, CR2GT, CR3GT, CR4GT, CR5GT, CR6GT, CR7GT]>;
+def : SubRegSet<sub_eq,
+ [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
+ [CR0EQ, CR1EQ, CR2EQ, CR3EQ, CR4EQ, CR5EQ, CR6EQ, CR7EQ]>;
+def : SubRegSet<sub_un,
+ [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
+ [CR0UN, CR1UN, CR2UN, CR3UN, CR4UN, CR5UN, CR6UN, CR7UN]>;
+
// Link register
def LR : SPR<8, "lr">, DwarfRegNum<[65]>;
//let Aliases = [LR] in
Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.td?rev=104660&r1=104659&r2=104660&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.td Tue May 25 20:21:14 2010
@@ -20,11 +20,6 @@
let Namespace = "SP";
}
-let Namespace = "SP" in {
-def sub_even : SubRegIndex;
-def sub_odd : SubRegIndex;
-}
-
// Registers are identified with 5-bit ID numbers.
// Ri - 32-bit integer registers
class Ri<bits<5> num, string n> : SparcReg<n> {
@@ -38,7 +33,6 @@
class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> {
let Num = num;
let SubRegs = subregs;
- let SubRegIndices = [sub_even, sub_odd];
}
// Control Registers
Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td?rev=104660&r1=104659&r2=104660&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td Tue May 25 20:21:14 2010
@@ -53,14 +53,6 @@
field bits<4> Num = num;
}
-let Namespace = "SystemZ" in {
-def subreg_32bit : SubRegIndex;
-def subreg_even32 : SubRegIndex;
-def subreg_odd32 : SubRegIndex;
-def subreg_even : SubRegIndex;
-def subreg_odd : SubRegIndex;
-}
-
// General-purpose registers
def R0W : GPR32< 0, "r0">, DwarfRegNum<[0]>;
def R1W : GPR32< 1, "r1">, DwarfRegNum<[1]>;
@@ -79,7 +71,6 @@
def R14W : GPR32<14, "r14">, DwarfRegNum<[14]>;
def R15W : GPR32<15, "r15">, DwarfRegNum<[15]>;
-let SubRegIndices = [subreg_32bit] in {
def R0D : GPR64< 0, "r0", [R0W]>, DwarfRegNum<[0]>;
def R1D : GPR64< 1, "r1", [R1W]>, DwarfRegNum<[1]>;
def R2D : GPR64< 2, "r2", [R2W]>, DwarfRegNum<[2]>;
@@ -96,10 +87,8 @@
def R13D : GPR64<13, "r13", [R13W]>, DwarfRegNum<[13]>;
def R14D : GPR64<14, "r14", [R14W]>, DwarfRegNum<[14]>;
def R15D : GPR64<15, "r15", [R15W]>, DwarfRegNum<[15]>;
-}
// Register pairs
-let SubRegIndices = [subreg_even32, subreg_odd32] in {
def R0P : GPR64< 0, "r0", [R0W, R1W], [R0D, R1D]>, DwarfRegNum<[0]>;
def R2P : GPR64< 2, "r2", [R2W, R3W], [R2D, R3D]>, DwarfRegNum<[2]>;
def R4P : GPR64< 4, "r4", [R4W, R5W], [R4D, R5D]>, DwarfRegNum<[4]>;
@@ -108,11 +97,7 @@
def R10P : GPR64<10, "r10", [R10W, R11W], [R10D, R11D]>, DwarfRegNum<[10]>;
def R12P : GPR64<12, "r12", [R12W, R13W], [R12D, R13D]>, DwarfRegNum<[12]>;
def R14P : GPR64<14, "r14", [R14W, R15W], [R14D, R15D]>, DwarfRegNum<[14]>;
-}
-let SubRegIndices = [subreg_even, subreg_odd],
- CompositeIndices = [(subreg_even32 subreg_even, subreg_32bit),
- (subreg_odd32 subreg_odd, subreg_32bit)] in {
def R0Q : GPR128< 0, "r0", [R0D, R1D], [R0P]>, DwarfRegNum<[0]>;
def R2Q : GPR128< 2, "r2", [R2D, R3D], [R2P]>, DwarfRegNum<[2]>;
def R4Q : GPR128< 4, "r4", [R4D, R5D], [R4P]>, DwarfRegNum<[4]>;
@@ -121,7 +106,6 @@
def R10Q : GPR128<10, "r10", [R10D, R11D], [R10P]>, DwarfRegNum<[10]>;
def R12Q : GPR128<12, "r12", [R12D, R13D], [R12P]>, DwarfRegNum<[12]>;
def R14Q : GPR128<14, "r14", [R14D, R15D], [R14P]>, DwarfRegNum<[14]>;
-}
// Floating-point registers
def F0S : FPRS< 0, "f0">, DwarfRegNum<[16]>;
@@ -141,7 +125,6 @@
def F14S : FPRS<14, "f14">, DwarfRegNum<[30]>;
def F15S : FPRS<15, "f15">, DwarfRegNum<[31]>;
-let SubRegIndices = [subreg_32bit] in {
def F0L : FPRL< 0, "f0", [F0S]>, DwarfRegNum<[16]>;
def F1L : FPRL< 1, "f1", [F1S]>, DwarfRegNum<[17]>;
def F2L : FPRL< 2, "f2", [F2S]>, DwarfRegNum<[18]>;
@@ -158,11 +141,41 @@
def F13L : FPRL<13, "f13", [F13S]>, DwarfRegNum<[29]>;
def F14L : FPRL<14, "f14", [F14S]>, DwarfRegNum<[30]>;
def F15L : FPRL<15, "f15", [F15S]>, DwarfRegNum<[31]>;
-}
// Status register
def PSW : SystemZReg<"psw">;
+let Namespace = "SystemZ" in {
+def subreg_32bit : SubRegIndex;
+def subreg_even32 : SubRegIndex;
+def subreg_odd32 : SubRegIndex;
+def subreg_even : SubRegIndex;
+def subreg_odd : SubRegIndex;
+}
+
+def : SubRegSet<subreg_32bit, [R0D, R1D, R2D, R3D, R4D, R5D, R6D, R7D,
+ R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
+ [R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W,
+ R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
+
+def : SubRegSet<subreg_even, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
+ [R0D, R2D, R4D, R6D, R8D, R10D, R12D, R14D]>;
+
+def : SubRegSet<subreg_odd, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
+ [R1D, R3D, R5D, R7D, R9D, R11D, R13D, R15D]>;
+
+def : SubRegSet<subreg_even32, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
+ [R0W, R2W, R4W, R6W, R8W, R10W, R12W, R14W]>;
+
+def : SubRegSet<subreg_odd32, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
+ [R1W, R3W, R5W, R7W, R9W, R11W, R13W, R15W]>;
+
+def : SubRegSet<subreg_even32, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
+ [R0W, R2W, R4W, R6W, R8W, R10W, R12W, R14W]>;
+
+def : SubRegSet<subreg_odd32, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
+ [R1W, R3W, R5W, R7W, R9W, R11W, R13W, R15W]>;
+
/// Register classes
def GR32 : RegisterClass<"SystemZ", [i32], 32,
// Volatile registers
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=104660&r1=104659&r2=104660&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Tue May 25 20:21:14 2010
@@ -68,22 +68,17 @@
def BH : Register<"bh">, DwarfRegNum<[3, 3, 3]>;
// 16-bit registers
- let SubRegIndices = [sub_8bit, sub_8bit_hi] in {
def AX : RegisterWithSubRegs<"ax", [AL,AH]>, DwarfRegNum<[0, 0, 0]>;
def DX : RegisterWithSubRegs<"dx", [DL,DH]>, DwarfRegNum<[1, 2, 2]>;
def CX : RegisterWithSubRegs<"cx", [CL,CH]>, DwarfRegNum<[2, 1, 1]>;
def BX : RegisterWithSubRegs<"bx", [BL,BH]>, DwarfRegNum<[3, 3, 3]>;
- }
- let SubRegIndices = [sub_8bit] in {
def SI : RegisterWithSubRegs<"si", [SIL]>, DwarfRegNum<[4, 6, 6]>;
def DI : RegisterWithSubRegs<"di", [DIL]>, DwarfRegNum<[5, 7, 7]>;
def BP : RegisterWithSubRegs<"bp", [BPL]>, DwarfRegNum<[6, 4, 5]>;
def SP : RegisterWithSubRegs<"sp", [SPL]>, DwarfRegNum<[7, 5, 4]>;
- }
def IP : Register<"ip">, DwarfRegNum<[16]>;
// X86-64 only
- let SubRegIndices = [sub_8bit] in {
def R8W : RegisterWithSubRegs<"r8w", [R8B]>, DwarfRegNum<[8, -2, -2]>;
def R9W : RegisterWithSubRegs<"r9w", [R9B]>, DwarfRegNum<[9, -2, -2]>;
def R10W : RegisterWithSubRegs<"r10w", [R10B]>, DwarfRegNum<[10, -2, -2]>;
@@ -92,9 +87,8 @@
def R13W : RegisterWithSubRegs<"r13w", [R13B]>, DwarfRegNum<[13, -2, -2]>;
def R14W : RegisterWithSubRegs<"r14w", [R14B]>, DwarfRegNum<[14, -2, -2]>;
def R15W : RegisterWithSubRegs<"r15w", [R15B]>, DwarfRegNum<[15, -2, -2]>;
- }
+
// 32-bit registers
- let SubRegIndices = [sub_16bit] in {
def EAX : RegisterWithSubRegs<"eax", [AX]>, DwarfRegNum<[0, 0, 0]>;
def EDX : RegisterWithSubRegs<"edx", [DX]>, DwarfRegNum<[1, 2, 2]>;
def ECX : RegisterWithSubRegs<"ecx", [CX]>, DwarfRegNum<[2, 1, 1]>;
@@ -114,10 +108,8 @@
def R13D : RegisterWithSubRegs<"r13d", [R13W]>, DwarfRegNum<[13, -2, -2]>;
def R14D : RegisterWithSubRegs<"r14d", [R14W]>, DwarfRegNum<[14, -2, -2]>;
def R15D : RegisterWithSubRegs<"r15d", [R15W]>, DwarfRegNum<[15, -2, -2]>;
- }
// 64-bit registers, X86-64 only
- let SubRegIndices = [sub_32bit] in {
def RAX : RegisterWithSubRegs<"rax", [EAX]>, DwarfRegNum<[0, -2, -2]>;
def RDX : RegisterWithSubRegs<"rdx", [EDX]>, DwarfRegNum<[1, -2, -2]>;
def RCX : RegisterWithSubRegs<"rcx", [ECX]>, DwarfRegNum<[2, -2, -2]>;
@@ -136,7 +128,6 @@
def R14 : RegisterWithSubRegs<"r14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
def R15 : RegisterWithSubRegs<"r15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
def RIP : RegisterWithSubRegs<"rip", [EIP]>, DwarfRegNum<[16, -2, -2]>;
- }
// MMX Registers. These are actually aliased to ST0 .. ST7
def MM0 : Register<"mm0">, DwarfRegNum<[41, 29, 29]>;
@@ -157,9 +148,7 @@
def FP5 : Register<"fp5">;
def FP6 : Register<"fp6">;
- // XMM Registers, used by the various SSE instruction set extensions.
- // The sub_ss and sub_sd subregs are the same registers with another regclass.
- let CompositeIndices = [(sub_ss), (sub_sd)] in {
+ // XMM Registers, used by the various SSE instruction set extensions
def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>;
def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>;
def XMM2: Register<"xmm2">, DwarfRegNum<[19, 23, 23]>;
@@ -178,10 +167,8 @@
def XMM13: Register<"xmm13">, DwarfRegNum<[30, -2, -2]>;
def XMM14: Register<"xmm14">, DwarfRegNum<[31, -2, -2]>;
def XMM15: Register<"xmm15">, DwarfRegNum<[32, -2, -2]>;
- }
// YMM Registers, used by AVX instructions
- let SubRegIndices = [sub_xmm] in {
def YMM0: RegisterWithSubRegs<"ymm0", [XMM0]>, DwarfRegNum<[17, 21, 21]>;
def YMM1: RegisterWithSubRegs<"ymm1", [XMM1]>, DwarfRegNum<[18, 22, 22]>;
def YMM2: RegisterWithSubRegs<"ymm2", [XMM2]>, DwarfRegNum<[19, 23, 23]>;
@@ -198,7 +185,6 @@
def YMM13: RegisterWithSubRegs<"ymm13", [XMM13]>, DwarfRegNum<[30, -2, -2]>;
def YMM14: RegisterWithSubRegs<"ymm14", [XMM14]>, DwarfRegNum<[31, -2, -2]>;
def YMM15: RegisterWithSubRegs<"ymm15", [XMM15]>, DwarfRegNum<[32, -2, -2]>;
- }
// Floating point stack registers
def ST0 : Register<"st(0)">, DwarfRegNum<[33, 12, 11]>;
@@ -245,6 +231,75 @@
//===----------------------------------------------------------------------===//
+// Subregister Set Definitions... now that we have all of the pieces, define the
+// sub registers for each register.
+//
+
+def : SubRegSet<sub_8bit, [AX, CX, DX, BX, SP, BP, SI, DI,
+ R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
+ [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
+ R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
+
+def : SubRegSet<sub_8bit_hi, [AX, CX, DX, BX],
+ [AH, CH, DH, BH]>;
+
+def : SubRegSet<sub_8bit, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
+ R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
+ [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
+ R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
+
+def : SubRegSet<sub_8bit_hi, [EAX, ECX, EDX, EBX],
+ [AH, CH, DH, BH]>;
+
+def : SubRegSet<sub_16bit, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
+ R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
+ [AX, CX, DX, BX, SP, BP, SI, DI,
+ R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
+
+def : SubRegSet<sub_8bit, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
+ R8, R9, R10, R11, R12, R13, R14, R15],
+ [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
+ R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
+
+def : SubRegSet<sub_8bit_hi, [RAX, RCX, RDX, RBX],
+ [AH, CH, DH, BH]>;
+
+def : SubRegSet<sub_16bit, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
+ R8, R9, R10, R11, R12, R13, R14, R15],
+ [AX, CX, DX, BX, SP, BP, SI, DI,
+ R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
+
+def : SubRegSet<sub_32bit, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
+ R8, R9, R10, R11, R12, R13, R14, R15],
+ [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
+ R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]>;
+
+def : SubRegSet<sub_ss, [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
+ YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15],
+ [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
+ XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
+
+def : SubRegSet<sub_sd, [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
+ YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15],
+ [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
+ XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
+
+def : SubRegSet<sub_xmm, [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
+ YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15],
+ [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
+ XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
+
+def : SubRegSet<sub_ss, [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
+ XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15],
+ [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
+ XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
+
+def : SubRegSet<sub_sd, [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
+ XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15],
+ [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
+ XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
+
+//===----------------------------------------------------------------------===//
// Register Class Definitions... now that we have all of the pieces, define the
// top-level register classes. The order specified in the register list is
// implicitly defined to be the register allocation order.
Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=104660&r1=104659&r2=104660&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Tue May 25 20:21:14 2010
@@ -171,67 +171,6 @@
addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
}
-// Map SubRegIndex -> Register
-typedef std::map<Record*, Record*, LessRecord> SubRegMap;
-// Map Register -> SubRegMap
-typedef std::map<Record*, SubRegMap> AllSubRegMap;
-
-// Calculate all subregindices for Reg. Loopy subregs cause infinite recursion.
-static SubRegMap &inferSubRegIndices(Record *Reg, AllSubRegMap &ASRM) {
- SubRegMap &SRM = ASRM[Reg];
- if (!SRM.empty())
- return SRM;
- std::vector<Record*> SubRegs = Reg->getValueAsListOfDefs("SubRegs");
- std::vector<Record*> Indices = Reg->getValueAsListOfDefs("SubRegIndices");
- if (SubRegs.size() != Indices.size())
- throw "Register " + Reg->getName() + " SubRegIndices doesn't match SubRegs";
-
- // First insert the direct subregs.
- for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
- if (!SRM.insert(std::make_pair(Indices[i], SubRegs[i])).second)
- throw "SubRegIndex " + Indices[i]->getName()
- + " appears twice in Register " + Reg->getName();
- inferSubRegIndices(SubRegs[i], ASRM);
- }
-
- // Clone inherited subregs. Here the order is important - earlier subregs take
- // precedence.
- for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
- SubRegMap &M = ASRM[SubRegs[i]];
- SRM.insert(M.begin(), M.end());
- }
-
- // Finally process the composites.
- ListInit *Comps = Reg->getValueAsListInit("CompositeIndices");
- for (unsigned i = 0, e = Comps->size(); i != e; ++i) {
- DagInit *Pat = dynamic_cast<DagInit*>(Comps->getElement(i));
- if (!Pat)
- throw "Invalid dag '" + Comps->getElement(i)->getAsString()
- + "' in CompositeIndices";
- DefInit *BaseIdxInit = dynamic_cast<DefInit*>(Pat->getOperator());
- if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex"))
- throw "Invalid SubClassIndex in " + Pat->getAsString();
-
- // Resolve list of subreg indices into R2.
- Record *R2 = Reg;
- for (DagInit::const_arg_iterator di = Pat->arg_begin(),
- de = Pat->arg_end(); di != de; ++di) {
- DefInit *IdxInit = dynamic_cast<DefInit*>(*di);
- if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
- throw "Invalid SubClassIndex in " + Pat->getAsString();
- SubRegMap::const_iterator ni = ASRM[R2].find(IdxInit->getDef());
- if (ni == ASRM[R2].end())
- throw "Composite " + Pat->getAsString() + " refers to bad index in "
- + R2->getName();
- R2 = ni->second;
- }
-
- // Insert composite index. Allow overriding inherited indices etc.
- SRM[BaseIdxInit->getDef()] = R2;
- }
- return SRM;
-}
-
class RegisterSorter {
private:
std::map<Record*, std::set<Record*>, LessRecord> &RegisterSubRegs;
@@ -516,6 +455,8 @@
std::map<Record*, std::set<Record*>, LessRecord> RegisterSubRegs;
std::map<Record*, std::set<Record*>, LessRecord> RegisterSuperRegs;
std::map<Record*, std::set<Record*>, LessRecord> RegisterAliases;
+ // Register -> [(SubRegIndex, Register)]
+ std::map<Record*, std::vector<std::pair<Record*, Record*> > > SubRegVectors;
typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
DwarfRegNumsMapTy DwarfRegNums;
@@ -807,44 +748,56 @@
std::string ClassName = Target.getName() + "GenRegisterInfo";
// Calculate the mapping of subregister+index pairs to physical registers.
- AllSubRegMap AllSRM;
-
+ std::vector<Record*> SubRegs = Records.getAllDerivedDefinitions("SubRegSet");
+ for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
+ Record *subRegIndex = SubRegs[i]->getValueAsDef("Index");
+ std::vector<Record*> From = SubRegs[i]->getValueAsListOfDefs("From");
+ std::vector<Record*> To = SubRegs[i]->getValueAsListOfDefs("To");
+
+ if (From.size() != To.size()) {
+ errs() << "Error: register list and sub-register list not of equal length"
+ << " in SubRegSet\n";
+ exit(1);
+ }
+
+ // For each entry in from/to vectors, insert the to register at index
+ for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii)
+ SubRegVectors[From[ii]].push_back(std::make_pair(subRegIndex, To[ii]));
+ }
+
// Emit the subregister + index mapping function based on the information
// calculated above.
- OS << "unsigned " << ClassName
+ OS << "unsigned " << ClassName
<< "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
<< " switch (RegNo) {\n"
<< " default:\n return 0;\n";
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- SubRegMap &SRM = inferSubRegIndices(Regs[i].TheDef, AllSRM);
- if (SRM.empty())
- continue;
- OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
+ for (std::map<Record*, std::vector<std::pair<Record*, Record*> > >::iterator
+ I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
+ OS << " case " << getQualifiedName(I->first) << ":\n";
OS << " switch (Index) {\n";
OS << " default: return 0;\n";
- for (SubRegMap::const_iterator ii = SRM.begin(), ie = SRM.end(); ii != ie;
- ++ii)
- OS << " case " << getQualifiedName(ii->first)
- << ": return " << getQualifiedName(ii->second) << ";\n";
+ for (unsigned i = 0, e = I->second.size(); i != e; ++i)
+ OS << " case "
+ << getQualifiedName((I->second)[i].first) << ": return "
+ << getQualifiedName((I->second)[i].second) << ";\n";
OS << " };\n" << " break;\n";
}
OS << " };\n";
OS << " return 0;\n";
OS << "}\n\n";
- OS << "unsigned " << ClassName
+ OS << "unsigned " << ClassName
<< "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
<< " switch (RegNo) {\n"
<< " default:\n return 0;\n";
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- SubRegMap &SRM = AllSRM[Regs[i].TheDef];
- if (SRM.empty())
- continue;
- OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
- for (SubRegMap::const_iterator ii = SRM.begin(), ie = SRM.end(); ii != ie;
- ++ii)
- OS << " if (SubRegNo == " << getQualifiedName(ii->second)
- << ") return " << getQualifiedName(ii->first) << ";\n";
+ for (std::map<Record*, std::vector<std::pair<Record*, Record*> > >::iterator
+ I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
+ OS << " case " << getQualifiedName(I->first) << ":\n";
+ for (unsigned i = 0, e = I->second.size(); i != e; ++i)
+ OS << " if (SubRegNo == "
+ << getQualifiedName((I->second)[i].second)
+ << ") return "
+ << getQualifiedName((I->second)[i].first) << ";\n";
OS << " return 0;\n";
}
OS << " };\n";
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