[llvm-commits] [llvm] r104455 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

[Bob Wilson]

Author: bwilson
Date: Sun May 23 00:42:31 2010
New Revision: 104455

URL: http://llvm.org/viewvc/llvm-project?rev=104455&view=rev
Log:
VDUP doesn't support vectors with 64-bit elements.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=104455&r1=104454&r2=104455&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Sun May 23 00:42:31 2010
@@ -2876,12 +2876,12 @@
     return SDValue();
 
   // Use VDUP for non-constant splats.
-  if (usesOnlyOneValue)
+  unsigned EltSize = VT.getVectorElementType().getSizeInBits();
+  if (usesOnlyOneValue && EltSize <= 32)
     return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
 
   // Vectors with 32- or 64-bit elements can be built by directly assigning
   // the subregisters.
-  unsigned EltSize = VT.getVectorElementType().getSizeInBits();
   if (EltSize >= 32) {
     // Do the expansion with floating-point types, since that is what the VFP
     // registers are defined to use, and since i64 is not legal.