[llvm-commits] [patch] - Bugfix for TargetLowering::SimplifySetCC

[Evzen Muller]

Hi all,

When I compile this code (clang generates something similar for bitfield
access):

target datalayout = "e-p:32:32-f64:32:32-i64:32:32-n32"
target triple = "arm-none-eabi"

define i32 @extend2bit_v2(i32 %val) {
entry:
  %0 = trunc i32 %val to i2                       ; <i2> [#uses=1]
  %1 = sext i2 %0 to i32                          ; <i32> [#uses=1]
  %2 = icmp eq i32 %1, 3                          ; <i1> [#uses=1]
  %3 = zext i1 %2 to i32                          ; <i32> [#uses=1]
  ret i32 %3
}

ARM codegen produces:
@ BB#0:                                 @ %entry
        and     r1, r0, #3
        mov     r0, #0
        cmp     r1, #3
        moveq   r0, #1
        bx      lr

This is not correct, because when %val == 3 this will return 1, but expected
result is 0 because i2 constant (3) should be sign-extended before icmp.

There is an optimization in TargetLowering::SimplifySetCC (around line 1790)
which works fine if C1 has more or less active bits than ExtSrcTyBits, but I
think that if C1.getActiveBits() == ExtSrcTyBits we should do normal
truncate/sign-extend.

Attached patch should fix this problem.

Thanks
Evzen

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