[llvm-commits] [llvm] r104108 - /llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp

[Daniel Dunbar]

Author: ddunbar
Date: Tue May 18 23:31:36 2010
New Revision: 104108

URL: http://llvm.org/viewvc/llvm-project?rev=104108&view=rev
Log:
MC/X86: Strip spurious operands from CALL64r as we do for CALL64pcrel32, to
avoid same prefix byte problem as in r104062.

Modified:
    llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp?rev=104108&r1=104107&r2=104108&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp Tue May 18 23:31:36 2010
@@ -329,18 +329,20 @@
     LowerSubReg32_Op0(OutMI, X86::MOV32r0);   // MOV64r0 -> MOV32r0
     LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
     break;
-    
-  // CALL64pcrel32 - This instruction has register inputs modeled as normal
-  // uses instead of implicit uses.  As such, truncate off all but the first
-  // operand (the callee).  FIXME: Change isel.
+
+  // CALL64r, CALL64pcrel32 - These instructions have register inputs modeled as
+  // normal uses instead of implicit uses.  As such, truncate off all but the
+  // first operand (the callee).  FIXME: Change isel.
+  case X86::CALL64r:
   case X86::CALL64pcrel32: {
+    unsigned Opcode = OutMI.getOpcode();
     MCOperand Saved = OutMI.getOperand(0);
     OutMI = MCInst();
-    OutMI.setOpcode(X86::CALL64pcrel32);
+    OutMI.setOpcode(Opcode);
     OutMI.addOperand(Saved);
     break;
   }
-      
+
   // The assembler backend wants to see branches in their small form and relax
   // them to their large form.  The JIT can only handle the large form because
   // it does not do relaxation.  For now, translate the large form to the