[llvm-commits] [llvm] r103935 - in /llvm/trunk: lib/CodeGen/RegAllocFast.cpp test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
Jakob Stoklund Olesen
stoklund at 2pi.dk
Sun May 16 21:50:57 PDT 2010
Author: stoklund
Date: Sun May 16 23:50:57 2010
New Revision: 103935
URL: http://llvm.org/viewvc/llvm-project?rev=103935&view=rev
Log:
Only use clairvoyance when defining a register, and then only if it has one use.
This makes allocation independent on the ordering of use-def chains.
Modified:
llvm/trunk/lib/CodeGen/RegAllocFast.cpp
llvm/trunk/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=103935&r1=103934&r2=103935&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Sun May 16 23:50:57 2010
@@ -399,20 +399,6 @@
!Allocatable.test(Hint)))
Hint = 0;
- // If there is no hint, peek at the first use of this register.
- if (!Hint && !MRI->use_nodbg_empty(VirtReg)) {
- MachineInstr &MI = *MRI->use_nodbg_begin(VirtReg);
- unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
- // Copy to physreg -> use physreg as hint.
- if (TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
- SrcReg == VirtReg && TargetRegisterInfo::isPhysicalRegister(DstReg) &&
- RC->contains(DstReg) && !UsedInInstr.test(DstReg) &&
- Allocatable.test(DstReg)) {
- Hint = DstReg;
- DEBUG(dbgs() << "%reg" << VirtReg << " gets hint from " << MI);
- }
- }
-
// Take hint when possible.
if (Hint) {
assert(RC->contains(Hint) && !UsedInInstr.test(Hint) &&
@@ -543,9 +529,18 @@
bool New;
tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg()));
LiveReg &LR = LRI->second;
- if (New)
+ if (New) {
+ // If there is no hint, peek at the only use of this register.
+ if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) &&
+ MRI->hasOneNonDBGUse(VirtReg)) {
+ unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
+ // It's a copy, use the destination register as a hint.
+ if (TII->isMoveInstr(*MRI->use_nodbg_begin(VirtReg),
+ SrcReg, DstReg, SrcSubReg, DstSubReg))
+ Hint = DstReg;
+ }
allocVirtReg(MI, *LRI, Hint);
- else
+ } else
addKillFlag(LR); // Kill before redefine.
assert(LR.PhysReg && "Register not assigned");
LR.LastUse = MI;
Modified: llvm/trunk/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll?rev=103935&r1=103934&r2=103935&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll Sun May 16 23:50:57 2010
@@ -1,15 +1,11 @@
; RUN: llc < %s | FileCheck %s
-; RUN: llc < %s -regalloc=local | FileCheck -check-prefix=LOCAL %s
-; RUN: llc < %s -regalloc=fast | FileCheck -check-prefix=FAST %s
+; RUN: llc < %s -regalloc=local | FileCheck %s
+; RUN: llc < %s -regalloc=fast | FileCheck %s
; The first argument of subfc must not be the same as any other register.
-; CHECK: subfc r3,r5,r4
-; CHECK: subfze r4,r6
-; LOCAL: subfc r6,r5,r4
-; LOCAL: subfze r3,r3
-; FAST: subfc r3,r5,r4
-; FAST: subfze r4,r6
-
+; CHECK: subfc [[REG:r.]],
+; CHECK-NOT: [[REG]]
+; CHECK: InlineAsm End
; PR1357
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
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