[llvm-commits] [llvm] r103881 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/mul_const.ll

[Evan Cheng]

On May 15, 2010, at 9:14 PM, Jakob Stoklund Olesen wrote:

> 
> On May 15, 2010, at 8:51 PM, Evan Cheng wrote:
> 
>> 
>> On May 15, 2010, at 5:36 PM, Jakob Stoklund Olesen wrote:
>>> AMD has suggested instruction sequences for factors 2-31 in §8.2:
>>> http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25112.PDF
>>> 
>>> A lot of them are shl+add and shl+sub which could be target independent, I guess. All of the power-of-two's are straight shl's, except for 2 which is better done with an add.
>> 
>> I am talking about power-of-two's ones. There is no good reason for these to be target dependent?
> 
> Translating (mul x, 2^N) -> (shl x, n) in the dag combiner sounds reasonable, and we are already doing that in DAGCombiner::visitMUL.
> 
> Then there is (mul x, 2^N+1) -> (add (shl x, n), x) and (mul x, 2^N-1) -> (sub (shl x, n), x). For these, X86 prefers to use LEA for factors 3, 5, and 9, so we are probably better off leaving that target dependent.

I would have preferred if dag combine does the transformation and x86 isel matches to the LEA. If it doesn't just work, then it's not a huge deal.

Anton, for ARM to only special case 3, 5, 7, and 9, that really bugs me. Please make it deal with pow-of-2 cases or I'll continue to nag about this. :-)

Evan

> 
> /Jakob
>