[llvm-commits] [llvm] r103855 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

[Evan Cheng]

Author: evancheng
Date: Fri May 14 21:20:21 2010
New Revision: 103855

URL: http://llvm.org/viewvc/llvm-project?rev=103855&view=rev
Log:
v4i64 and v8i64 are only synthesizable when NEON is available.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=103855&r1=103854&r2=103855&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri May 14 21:20:21 2010
@@ -585,10 +585,12 @@
   // Map v4i64 to QQ registers but do not make the type legal. Similarly map
   // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
   // load / store 4 to 8 consecutive D registers.
-  if (VT == MVT::v4i64)
-    return ARM::QQPRRegisterClass;
-  else if (VT == MVT::v8i64)
-    return ARM::QQQQPRRegisterClass;
+  if (Subtarget->hasNEON()) {
+    if (VT == MVT::v4i64)
+      return ARM::QQPRRegisterClass;
+    else if (VT == MVT::v8i64)
+      return ARM::QQQQPRRegisterClass;
+  }
   return TargetLowering::getRegClassFor(VT);
 }