[llvm-commits] [llvm] r102493 - in /llvm/trunk: lib/Target/X86/ test/CodeGen/X86/

Evan Cheng evan.cheng at apple.com
Wed Apr 28 10:35:52 PDT 2010


I can't debug dragonegg since we are not allowed to touch newer version of gcc in any way. Duncan, please get me a bitcode file test case. Thanks.

Evan

On Apr 28, 2010, at 10:20 AM, Dan Gohman wrote:

> Hi Evan,
> 
> This commit broke the dragonegg-x86_64-linux buildbot:
> 
> http://google1.osuosl.org:8011/builders/dragonegg-x86_64-linux/builds/893
> 
> The error looks like this:
> 
> llvm[4]: Compiling SPUAsmPrinter.cpp for Release build
> /tmp/ccSgkYx3.s: Assembler messages:
> /tmp/ccSgkYx3.s:634: Error: suffix or operands invalid for `mov'
> make[4]: *** [/home/baldrick/zorg/buildbot/osuosl/slave/dragonegg-x86_64-linux/llvm-build-1/lib/Target/CellSPU/AsmPrinter/Release/SPUAsmPrinter.o] Error 1
> make[4]: Leaving directory `/home/baldrick/zorg/buildbot/osuosl/slave/dragonegg-x86_64-linux/llvm-build-1/lib/Target/CellSPU/AsmPrinter'
> 
> Can you investigate?
> 
> Thanks,
> 
> Dan
> 
> On Apr 28, 2010, at 1:30 AM, Evan Cheng wrote:
> 
>> Author: evancheng
>> Date: Wed Apr 28 03:30:49 2010
>> New Revision: 102493
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=102493&view=rev
>> Log:
>> Enable i16 to i32 promotion by default.
>> 
>> Added:
>>   llvm/trunk/test/CodeGen/X86/promote-i16.ll
>> Modified:
>>   llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
>>   llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>>   llvm/trunk/lib/Target/X86/X86Instr64bit.td
>>   llvm/trunk/lib/Target/X86/X86InstrInfo.td
>>   llvm/trunk/lib/Target/X86/X86Subtarget.cpp
>>   llvm/trunk/lib/Target/X86/X86Subtarget.h
>>   llvm/trunk/test/CodeGen/X86/2008-07-11-SpillerBug.ll
>>   llvm/trunk/test/CodeGen/X86/2008-10-16-SpillerBug.ll
>>   llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll
>>   llvm/trunk/test/CodeGen/X86/atomic_add.ll
>>   llvm/trunk/test/CodeGen/X86/h-registers-0.ll
>>   llvm/trunk/test/CodeGen/X86/ins_subreg_coalesce-1.ll
>>   llvm/trunk/test/CodeGen/X86/store-narrow.ll
>>   llvm/trunk/test/CodeGen/X86/tls11.ll
>>   llvm/trunk/test/CodeGen/X86/xor.ll
>> 
>> Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=102493&r1=102492&r2=102493&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Apr 28 03:30:49 2010
>> @@ -1854,6 +1854,9 @@
>> 
>>    // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
>>    // use a smaller encoding.
>> +    if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse())
>> +      // Look past the truncate if CMP is the only use of it.
>> +      N0 = N0.getOperand(0);
>>    if (N0.getNode()->getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
>>        N0.getValueType() != MVT::i8 &&
>>        X86::isZeroNode(N1)) {
>> 
>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=102493&r1=102492&r2=102493&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Apr 28 03:30:49 2010
>> @@ -6075,7 +6075,7 @@
>>    // the encoding for the i16 version is larger than the i32 version.
>>    // Also promote i16 to i32 for performance / code size reason.
>>    if (LHS.getValueType() == MVT::i8 ||
>> -        (Subtarget->shouldPromote16Bit() && LHS.getValueType() == MVT::i16))
>> +        LHS.getValueType() == MVT::i16)
>>      LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
>> 
>>    // If the operand types disagree, extend the shift amount to match.  Since
>> @@ -9949,7 +9949,7 @@
>> bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
>>  if (!isTypeLegal(VT))
>>    return false;
>> -  if (!Subtarget->shouldPromote16Bit() || VT != MVT::i16)
>> +  if (VT != MVT::i16)
>>    return true;
>> 
>>  switch (Opc) {
>> @@ -9983,9 +9983,6 @@
>> /// beneficial for dag combiner to promote the specified node. If true, it
>> /// should return the desired promotion type by reference.
>> bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
>> -  if (!Subtarget->shouldPromote16Bit())
>> -    return false;
>> -
>>  EVT VT = Op.getValueType();
>>  if (VT != MVT::i16)
>>    return false;
>> @@ -9998,10 +9995,16 @@
>>    LoadSDNode *LD = cast<LoadSDNode>(Op);
>>    // If the non-extending load has a single use and it's not live out, then it
>>    // might be folded.
>> -    if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
>> -        Op.hasOneUse() &&
>> -        Op.getNode()->use_begin()->getOpcode() != ISD::CopyToReg)
>> -      return false;
>> +    if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
>> +                                                     Op.hasOneUse()*/) {
>> +      for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
>> +             UE = Op.getNode()->use_end(); UI != UE; ++UI) {
>> +        // The only case where we'd want to promote LOAD (rather then it being
>> +        // promoted as an operand is when it's only use is liveout.
>> +        if (UI->getOpcode() != ISD::CopyToReg)
>> +          return false;
>> +      }
>> +    }
>>    Promote = true;
>>    break;
>>  }
>> @@ -10011,8 +10014,7 @@
>>    Promote = true;
>>    break;
>>  case ISD::SHL:
>> -  case ISD::SRL:
>> - {
>> +  case ISD::SRL: {
>>    SDValue N0 = Op.getOperand(0);
>>    // Look out for (store (shl (load), x)).
>>    if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
>> 
>> Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=102493&r1=102492&r2=102493&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
>> +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Wed Apr 28 03:30:49 2010
>> @@ -2086,6 +2086,11 @@
>>            (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
>>                            x86_subreg_8bit_hi))>,
>>      Requires<[In64BitMode]>;
>> +def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
>> +          (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 
>> +                                                                   GR32_ABCD)),
>> +                                             x86_subreg_8bit_hi))>,
>> +      Requires<[In64BitMode]>;
>> def : Pat<(srl GR16:$src, (i8 8)),
>>          (EXTRACT_SUBREG
>>            (MOVZX32_NOREXrr8
>> 
>> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=102493&r1=102492&r2=102493&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
>> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed Apr 28 03:30:49 2010
>> @@ -331,8 +331,6 @@
>> def FastBTMem    : Predicate<"!Subtarget->isBTMemSlow()">;
>> def CallImmAddr  : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
>> def HasAES       : Predicate<"Subtarget->hasAES()">;
>> -def Promote16Bit : Predicate<"Subtarget->shouldPromote16Bit()">;
>> -def NotPromote16Bit : Predicate<"!Subtarget->shouldPromote16Bit()">;
>> 
>> //===----------------------------------------------------------------------===//
>> // X86 Instruction Format Definitions.
>> @@ -4450,12 +4448,10 @@
>> // avoid partial-register updates.
>> def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8  GR8 :$src)>;
>> def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8  GR8 :$src)>;
>> -def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>,
>> -          Requires<[NotPromote16Bit]>;
>> 
>> +// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
>> def : Pat<(i32 (anyext GR16:$src)),
>> -          (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>,
>> -          Requires<[Promote16Bit]>;
>> +          (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
>> 
>> 
>> //===----------------------------------------------------------------------===//
>> @@ -4546,6 +4542,11 @@
>>                                                             GR32_ABCD)),
>>                                      x86_subreg_8bit_hi))>,
>>      Requires<[In32BitMode]>;
>> +def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
>> +          (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 
>> +                                                             GR32_ABCD)),
>> +                                      x86_subreg_8bit_hi))>,
>> +      Requires<[In32BitMode]>;
>> 
>> // (shl x, 1) ==> (add x, x)
>> def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr  GR8 :$src1, GR8 :$src1)>;
>> 
>> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=102493&r1=102492&r2=102493&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Wed Apr 28 03:30:49 2010
>> @@ -16,7 +16,6 @@
>> #include "X86InstrInfo.h"
>> #include "X86GenSubtarget.inc"
>> #include "llvm/GlobalValue.h"
>> -#include "llvm/Support/CommandLine.h"
>> #include "llvm/Support/Debug.h"
>> #include "llvm/Support/raw_ostream.h"
>> #include "llvm/System/Host.h"
>> @@ -25,10 +24,6 @@
>> #include "llvm/ADT/SmallVector.h"
>> using namespace llvm;
>> 
>> -static cl::opt<bool>
>> -DoPromote16Bit("promote-16bit", cl::Hidden,
>> -               cl::desc("Promote 16-bit instructions"));
>> -
>> #if defined(_MSC_VER)
>> #include <intrin.h>
>> #endif
>> @@ -298,7 +293,6 @@
>>  , IsBTMemSlow(false)
>>  , IsUAMemFast(false)
>>  , HasVectorUAMem(false)
>> -  , Promote16Bit(DoPromote16Bit)
>>  , DarwinVers(0)
>>  , stackAlignment(8)
>>  // FIXME: this is a known good value for Yonah. How about others?
>> 
>> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=102493&r1=102492&r2=102493&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
>> +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Wed Apr 28 03:30:49 2010
>> @@ -88,10 +88,6 @@
>>  /// operands. This may require setting a feature bit in the processor.
>>  bool HasVectorUAMem;
>> 
>> -  /// Promote16Bit - True if codegen should promote 16-bit operations to 32-bit.
>> -  /// This is a temporary option.
>> -  bool Promote16Bit;
>> -
>>  /// DarwinVers - Nonzero if this is a darwin platform: the numeric
>>  /// version of the platform, e.g. 8 = 10.4 (Tiger), 9 = 10.5 (Leopard), etc.
>>  unsigned char DarwinVers; // Is any darwin-x86 platform.
>> @@ -160,7 +156,6 @@
>>  bool isBTMemSlow() const { return IsBTMemSlow; }
>>  bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
>>  bool hasVectorUAMem() const { return HasVectorUAMem; }
>> -  bool shouldPromote16Bit() const { return Promote16Bit; }
>> 
>>  bool isTargetDarwin() const { return TargetType == isDarwin; }
>>  bool isTargetELF() const { return TargetType == isELF; }
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/2008-07-11-SpillerBug.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-07-11-SpillerBug.ll?rev=102493&r1=102492&r2=102493&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/2008-07-11-SpillerBug.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/2008-07-11-SpillerBug.ll Wed Apr 28 03:30:49 2010
>> @@ -3,6 +3,7 @@
>> 
>> ; CHECK: andl    $65534, %
>> ; CHECK-NEXT: movl %
>> +; CHECK-NEXT: movzwl
>> ; CHECK-NEXT: movl $17
>> 
>> @g_5 = external global i16		; <i16*> [#uses=2]
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/2008-10-16-SpillerBug.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-10-16-SpillerBug.ll?rev=102493&r1=102492&r2=102493&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/2008-10-16-SpillerBug.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/2008-10-16-SpillerBug.ll Wed Apr 28 03:30:49 2010
>> @@ -1,4 +1,4 @@
>> -; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin -stats |& grep asm-printer | grep 40
>> +; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin -stats |& grep asm-printer | grep 41
>> ; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin | FileCheck %s
>> 
>> 	%struct.XXDActiveTextureTargets = type { i64, i64, i64, i64, i64, i64 }
>> @@ -63,13 +63,13 @@
>> define void @t(%struct.XXDState* %gldst, <4 x float>* %prgrm, <4 x float>** %buffs, %struct._XXVMConstants* %cnstn, %struct.YYToken* %pstrm, %struct.XXVMVPContext* %vmctx, %struct.XXVMTextures* %txtrs, %struct.XXVMVPStack* %vpstk, <4 x float>* %atr0, <4 x float>* %atr1, <4 x float>* %atr2, <4 x float>* %atr3, <4 x float>* %vtx0, <4 x float>* %vtx1, <4 x float>* %vtx2, <4 x float>* %vtx3, [4 x <4 x float>]* %tmpGbl, i32* %oldMsk, <4 x i32>* %adrGbl, i64 %key_token) nounwind {
>> entry:
>> ; CHECK: t:
>> -; CHECK: xorl %ecx, %ecx
>> 	%0 = trunc i64 %key_token to i32		; <i32> [#uses=1]
>> 	%1 = getelementptr %struct.YYToken* %pstrm, i32 %0		; <%struct.YYToken*> [#uses=5]
>> 	br label %bb1132
>> 
>> bb51:		; preds = %bb1132
>> ; CHECK: .align 4
>> +; CHECK: xorl %ecx, %ecx
>> ; CHECK: andl $7
>> 	%2 = getelementptr %struct.YYToken* %1, i32 %operation.0.rec, i32 0, i32 0		; <i16*> [#uses=1]
>> 	%3 = load i16* %2, align 1		; <i16> [#uses=3]
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll?rev=102493&r1=102492&r2=102493&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll Wed Apr 28 03:30:49 2010
>> @@ -4,7 +4,7 @@
>> ; rdar://6808032
>> 
>> ; CHECK: pextrw $14
>> -; CHECK-NEXT: movzbl
>> +; CHECK-NEXT: shrl $8
>> ; CHECK-NEXT: (%ebp)
>> ; CHECK-NEXT: pinsrw
>> 
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/atomic_add.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/atomic_add.ll?rev=102493&r1=102492&r2=102493&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/atomic_add.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/atomic_add.ll Wed Apr 28 03:30:49 2010
>> @@ -192,7 +192,7 @@
>> define void @sub2(i16* nocapture %p, i32 %v) nounwind ssp {
>> entry:
>> ; CHECK: sub2:
>> -; CHECK: subw
>> +; CHECK: negl
>> 	%0 = trunc i32 %v to i16		; <i16> [#uses=1]
>> 	%1 = tail call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %p, i16 %0)		; <i16> [#uses=0]
>> 	ret void
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/h-registers-0.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/h-registers-0.ll?rev=102493&r1=102492&r2=102493&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/h-registers-0.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/h-registers-0.ll Wed Apr 28 03:30:49 2010
>> @@ -1,12 +1,16 @@
>> -; RUN: llc < %s -march=x86-64 | grep {movzbl	%\[abcd\]h,} | count 4
>> -; RUN: llc < %s -march=x86    > %t
>> -; RUN: grep {incb	%ah} %t | count 3
>> -; RUN: grep {movzbl	%ah,} %t | count 3
>> +; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=X86-64
>> +; RUN: llc < %s -march=x86    | FileCheck %s -check-prefix=X86-32
>> 
>> ; Use h registers. On x86-64, codegen doesn't support general allocation
>> ; of h registers yet, due to x86 encoding complications.
>> 
>> define void @bar64(i64 inreg %x, i8* inreg %p) nounwind {
>> +; X86-64: bar64:
>> +; X86-64: shrq $8, %rdi
>> +; X86-64: incb %dil
>> +
>> +; X86-32: bar64:
>> +; X86-32: incb %ah
>>  %t0 = lshr i64 %x, 8
>>  %t1 = trunc i64 %t0 to i8
>>  %t2 = add i8 %t1, 1
>> @@ -15,6 +19,12 @@
>> }
>> 
>> define void @bar32(i32 inreg %x, i8* inreg %p) nounwind {
>> +; X86-64: bar32:
>> +; X86-64: shrl $8, %edi
>> +; X86-64: incb %dil
>> +
>> +; X86-32: bar32:
>> +; X86-32: incb %ah
>>  %t0 = lshr i32 %x, 8
>>  %t1 = trunc i32 %t0 to i8
>>  %t2 = add i8 %t1, 1
>> @@ -23,6 +33,12 @@
>> }
>> 
>> define void @bar16(i16 inreg %x, i8* inreg %p) nounwind {
>> +; X86-64: bar16:
>> +; X86-64: shrl $8, %edi
>> +; X86-64: incb %dil
>> +
>> +; X86-32: bar16:
>> +; X86-32: incb %ah
>>  %t0 = lshr i16 %x, 8
>>  %t1 = trunc i16 %t0 to i8
>>  %t2 = add i8 %t1, 1
>> @@ -31,18 +47,36 @@
>> }
>> 
>> define i64 @qux64(i64 inreg %x) nounwind {
>> +; X86-64: qux64:
>> +; X86-64: movq %rdi, %rax
>> +; X86-64: movzbl %ah, %eax
>> +
>> +; X86-32: qux64:
>> +; X86-32: movzbl %ah, %eax
>>  %t0 = lshr i64 %x, 8
>>  %t1 = and i64 %t0, 255
>>  ret i64 %t1
>> }
>> 
>> define i32 @qux32(i32 inreg %x) nounwind {
>> +; X86-64: qux32:
>> +; X86-64: movl %edi, %eax
>> +; X86-64: movzbl %ah, %eax
>> +
>> +; X86-32: qux32:
>> +; X86-32: movzbl %ah, %eax
>>  %t0 = lshr i32 %x, 8
>>  %t1 = and i32 %t0, 255
>>  ret i32 %t1
>> }
>> 
>> define i16 @qux16(i16 inreg %x) nounwind {
>> +; X86-64: qux16:
>> +; X86-64: movl %edi, %eax
>> +; X86-64: movzbl %ah, %eax
>> +
>> +; X86-32: qux16:
>> +; X86-32: movzbl %ah, %eax
>>  %t0 = lshr i16 %x, 8
>>  ret i16 %t0
>> }
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/ins_subreg_coalesce-1.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ins_subreg_coalesce-1.ll?rev=102493&r1=102492&r2=102493&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/ins_subreg_coalesce-1.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/ins_subreg_coalesce-1.ll Wed Apr 28 03:30:49 2010
>> @@ -1,7 +1,13 @@
>> -; RUN: llc < %s -march=x86 | grep mov | count 3
>> +; RUN: llc < %s -march=x86 | FileCheck %s
>> 
>> -define fastcc i32 @sqlite3ExprResolveNames() nounwind  {
>> +define fastcc i32 @t() nounwind  {
>> entry:
>> +; CHECK: t:
>> +; CHECK: movzwl 0, %eax
>> +; CHECK: orl $2, %eax
>> +; CHECK: movw %ax, 0
>> +; CHECK: shrl $3, %eax
>> +; CHECK: andl $1, %eax
>> 	br i1 false, label %UnifiedReturnBlock, label %bb4
>> bb4:		; preds = %entry
>> 	br i1 false, label %bb17, label %bb22
>> 
>> Added: llvm/trunk/test/CodeGen/X86/promote-i16.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/promote-i16.ll?rev=102493&view=auto
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/promote-i16.ll (added)
>> +++ llvm/trunk/test/CodeGen/X86/promote-i16.ll Wed Apr 28 03:30:49 2010
>> @@ -0,0 +1,11 @@
>> +; RUN: llc < %s -march=x86 | FileCheck %s
>> +
>> +define signext i16 @foo(i16 signext %x) nounwind {
>> +entry:
>> +; CHECK: foo:
>> +; CHECK: movzwl 4(%esp), %eax
>> +; CHECK: xorl $21998, %eax
>> +; CHECK: movswl %ax, %eax
>> +  %0 = xor i16 %x, 21998
>> +  ret i16 %0
>> +}
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/store-narrow.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/store-narrow.ll?rev=102493&r1=102492&r2=102493&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/store-narrow.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/store-narrow.ll Wed Apr 28 03:30:49 2010
>> @@ -67,7 +67,7 @@
>> ; X64: movw	%si, 2(%rdi)
>> 
>> ; X32: test4:
>> -; X32: movw	8(%esp), %ax
>> +; X32: movzwl	8(%esp), %eax
>> ; X32: movw	%ax, 2(%{{.*}})
>> }
>> 
>> @@ -84,7 +84,7 @@
>> ; X64: movw	%si, 2(%rdi)
>> 
>> ; X32: test5:
>> -; X32: movw	8(%esp), %ax
>> +; X32: movzwl	8(%esp), %eax
>> ; X32: movw	%ax, 2(%{{.*}})
>> }
>> 
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/tls11.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls11.ll?rev=102493&r1=102492&r2=102493&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/tls11.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/tls11.ll Wed Apr 28 03:30:49 2010
>> @@ -1,7 +1,7 @@
>> ; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
>> -; RUN: grep {movw	%gs:i at NTPOFF, %ax} %t
>> +; RUN: grep {movzwl	%gs:i at NTPOFF, %eax} %t
>> ; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
>> -; RUN: grep {movw	%fs:i at TPOFF, %ax} %t2
>> +; RUN: grep {movzwl	%fs:i at TPOFF, %eax} %t2
>> 
>> @i = thread_local global i16 15
>> 
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/xor.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/xor.ll?rev=102493&r1=102492&r2=102493&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/xor.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/xor.ll Wed Apr 28 03:30:49 2010
>> @@ -80,11 +80,11 @@
>> bb12:
>> 	ret i16 %tmp3
>> ; X64: test5:
>> -; X64:    notw	[[REG:%[a-z]+]]
>> -; X64:    andw	{{.*}}[[REG]]
>> +; X64:    notl	[[REG:%[a-z]+]]
>> +; X64:    andl	{{.*}}[[REG]]
>> ; X32: test5:
>> -; X32:    notw	[[REG:%[a-z]+]]
>> -; X32:    andw	{{.*}}[[REG]]
>> +; X32:    notl	[[REG:%[a-z]+]]
>> +; X32:    andl	{{.*}}[[REG]]
>> }
>> 
>> define i8 @test6(i8 %a, i8 %b) nounwind  {
>> 
>> 
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