[llvm-commits] [llvm] r99501 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

[Evan Cheng]

Author: evancheng
Date: Thu Mar 25 02:16:57 2010
New Revision: 99501

URL: http://llvm.org/viewvc/llvm-project?rev=99501&view=rev
Log:
Scheduler assumes SDDbgValue nodes are in source order. That's true currently. But add an assertion to verify it.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=99501&r1=99500&r2=99501&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Thu Mar 25 02:16:57 2010
@@ -528,8 +528,16 @@
       if (!MI)
         continue;
       MachineBasicBlock *MIBB = MI->getParent();
+#ifndef NDEBUG
+      unsigned LastDIOrder = 0;
+#endif
       for (; DI != DE &&
              (*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) {
+#ifndef NDEBUG
+        assert((*DI)->getOrder() >= LastDIOrder &&
+               "SDDbgValue nodes must be in source order!");
+        LastDIOrder = (*DI)->getOrder();
+#endif
         if ((*DI)->isInvalidated())
           continue;
         MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, MIBB, VRBaseMap, EM);