[llvm-commits] [llvm] r99376 - /llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

[Johnny Chen]

I think they should have a 2-register format for semantic reason.
The decoder has already gone through the hassle of recognizing
that Vm == Vn and return an Opcode of VMOVDneon/VMOVQ.

There are 14 consumers of N3VX, only two of them have exceptional meanings.
I can change the disassembler code to special case VMOVDneon/VMOVQ when dealing
with 3-register format instructions if you insist thay both should be 3-register format instructions.

On Mar 24, 2010, at 10:36 AM, Bob Wilson wrote:

> 
> On Mar 24, 2010, at 10:30 AM, Bob Wilson wrote:
> 
>> Please add a format argument to the N3VX class and use that here instead of this "let" assignment.
> 
> Hold that thought.  VMOVDneon and VMOVQ are not standard 2-register format instructions.  The "M" and "Vm" encoding fields are duplicated and must be consistent.  From an encoding perspective, "VMOV Vd, Vm" is equivalent to "VORR Vd, Vm, Vn" where m == n.
> 
> How do you intend to handle these instructions?  I think they should have a 3-register format and then add a special case in the encoding/decoding functions to distinguish VMOV from VORR.
> 
>> 
>> On Mar 23, 2010, at 6:29 PM, Johnny Chen wrote:
>> 
>>> Author: johnny
>>> Date: Tue Mar 23 20:29:25 2010
>>> New Revision: 99376
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=99376&view=rev
>>> Log:
>>> Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler.
>>> 
>>> Modified:
>>>  llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99376&r1=99375&r2=99376&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Mar 23 20:29:25 2010
>>> @@ -2778,10 +2778,13 @@
>>> 
>>> //   VMOV     : Vector Move (Register)
>>> 
>>> +// Mark these as 2-register instructions to help the disassembler.
>>> +let F = N2RegFrm, Form = N2RegFrm.Value in {
>>> def  VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
>>> -                    IIC_VMOVD, "vmov", "$dst, $src", "", []>;
>>> +                     IIC_VMOVD, "vmov", "$dst, $src", "", []>;
>>> def  VMOVQ    : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
>>> -                    IIC_VMOVD, "vmov", "$dst, $src", "", []>;
>>> +                     IIC_VMOVD, "vmov", "$dst, $src", "", []>;
>>> +}
>>> 
>>> //   VMOV     : Vector Move (Immediate)
>>> 
>>> 
>>> 
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