[llvm-commits] [llvm] r98810 - in /llvm/trunk: lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h test/CodeGen/X86/2007-01-08-InstrSched.ll test/CodeGen/X86/lsr-reuse.ll test/CodeGen/X86/sse2.ll test/CodeGen/X86/sse3.ll
Evan Cheng
evan.cheng at apple.com
Wed Mar 17 23:55:42 PDT 2010
Author: evancheng
Date: Thu Mar 18 01:55:42 2010
New Revision: 98810
URL: http://llvm.org/viewvc/llvm-project?rev=98810&view=rev
Log:
Turning off post-ra scheduling for x86. It isn't a consistent win.
Modified:
llvm/trunk/lib/Target/X86/X86Subtarget.cpp
llvm/trunk/lib/Target/X86/X86Subtarget.h
llvm/trunk/test/CodeGen/X86/2007-01-08-InstrSched.ll
llvm/trunk/test/CodeGen/X86/lsr-reuse.ll
llvm/trunk/test/CodeGen/X86/sse2.ll
llvm/trunk/test/CodeGen/X86/sse3.ll
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=98810&r1=98809&r2=98810&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Thu Mar 18 01:55:42 2010
@@ -366,12 +366,3 @@
if (StackAlignment)
stackAlignment = StackAlignment;
}
-
-bool X86Subtarget::enablePostRAScheduler(
- CodeGenOpt::Level OptLevel,
- TargetSubtarget::AntiDepBreakMode& Mode,
- RegClassVector& CriticalPathRCs) const {
- Mode = TargetSubtarget::ANTIDEP_CRITICAL;
- CriticalPathRCs.clear();
- return OptLevel >= CodeGenOpt::Aggressive;
-}
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=98810&r1=98809&r2=98810&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Thu Mar 18 01:55:42 2010
@@ -230,12 +230,6 @@
/// indicating the number of scheduling cycles of backscheduling that
/// should be attempted.
unsigned getSpecialAddressLatency() const;
-
- /// enablePostRAScheduler - X86 target is enabling post-alloc scheduling
- /// at 'More' optimization level.
- bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
- TargetSubtarget::AntiDepBreakMode& Mode,
- RegClassVector& CriticalPathRCs) const;
};
} // End llvm namespace
Modified: llvm/trunk/test/CodeGen/X86/2007-01-08-InstrSched.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2007-01-08-InstrSched.ll?rev=98810&r1=98809&r2=98810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2007-01-08-InstrSched.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2007-01-08-InstrSched.ll Thu Mar 18 01:55:42 2010
@@ -11,12 +11,12 @@
%tmp14 = fadd float %tmp12, %tmp7
ret float %tmp14
-; CHECK: mulss LCPI1_3(%rip)
-; CHECK-NEXT: mulss LCPI1_0(%rip)
-; CHECK-NEXT: mulss LCPI1_1(%rip)
-; CHECK-NEXT: mulss LCPI1_2(%rip)
-; CHECK-NEXT: addss
-; CHECK-NEXT: addss
-; CHECK-NEXT: addss
-; CHECK-NEXT: ret
+; CHECK: mulss LCPI1_0(%rip)
+; CHECK: mulss LCPI1_1(%rip)
+; CHECK: addss
+; CHECK: mulss LCPI1_2(%rip)
+; CHECK: addss
+; CHECK: mulss LCPI1_3(%rip)
+; CHECK: addss
+; CHECK: ret
}
Modified: llvm/trunk/test/CodeGen/X86/lsr-reuse.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lsr-reuse.ll?rev=98810&r1=98809&r2=98810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/lsr-reuse.ll (original)
+++ llvm/trunk/test/CodeGen/X86/lsr-reuse.ll Thu Mar 18 01:55:42 2010
@@ -8,10 +8,10 @@
; CHECK: full_me_0:
; CHECK: movsd (%rsi), %xmm0
-; CHECK: addq $8, %rsi
; CHECK: mulsd (%rdx), %xmm0
-; CHECK: addq $8, %rdx
; CHECK: movsd %xmm0, (%rdi)
+; CHECK: addq $8, %rsi
+; CHECK: addq $8, %rdx
; CHECK: addq $8, %rdi
; CHECK: decq %rcx
; CHECK: jne
@@ -53,10 +53,10 @@
; CHECK: mulsd -2048(%rdx), %xmm0
; CHECK: movsd %xmm0, -2048(%rdi)
; CHECK: movsd (%rsi), %xmm0
-; CHECK: addq $8, %rsi
; CHECK: divsd (%rdx), %xmm0
-; CHECK: addq $8, %rdx
; CHECK: movsd %xmm0, (%rdi)
+; CHECK: addq $8, %rsi
+; CHECK: addq $8, %rdx
; CHECK: addq $8, %rdi
; CHECK: decq %rcx
; CHECK: jne
@@ -99,10 +99,10 @@
; CHECK: mulsd (%rdx), %xmm0
; CHECK: movsd %xmm0, (%rdi)
; CHECK: movsd -2048(%rsi), %xmm0
-; CHECK: addq $8, %rsi
; CHECK: divsd -2048(%rdx), %xmm0
-; CHECK: addq $8, %rdx
; CHECK: movsd %xmm0, -2048(%rdi)
+; CHECK: addq $8, %rsi
+; CHECK: addq $8, %rdx
; CHECK: addq $8, %rdi
; CHECK: decq %rcx
; CHECK: jne
@@ -144,10 +144,10 @@
; CHECK: mulsd (%rdx), %xmm0
; CHECK: movsd %xmm0, (%rdi)
; CHECK: movsd -4096(%rsi), %xmm0
-; CHECK: addq $8, %rsi
; CHECK: divsd -4096(%rdx), %xmm0
-; CHECK: addq $8, %rdx
; CHECK: movsd %xmm0, -4096(%rdi)
+; CHECK: addq $8, %rsi
+; CHECK: addq $8, %rdx
; CHECK: addq $8, %rdi
; CHECK: decq %rcx
; CHECK: jne
@@ -310,10 +310,10 @@
; CHECK: addsd (%rsi), %xmm0
; CHECK: movsd %xmm0, (%rdx)
; CHECK: movsd 40(%rdi), %xmm0
-; CHECK: addq $8, %rdi
; CHECK: subsd 40(%rsi), %xmm0
-; CHECK: addq $8, %rsi
; CHECK: movsd %xmm0, 40(%rdx)
+; CHECK: addq $8, %rdi
+; CHECK: addq $8, %rsi
; CHECK: addq $8, %rdx
; CHECK: decq %rcx
; CHECK: jne
Modified: llvm/trunk/test/CodeGen/X86/sse2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2.ll?rev=98810&r1=98809&r2=98810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse2.ll Thu Mar 18 01:55:42 2010
@@ -10,10 +10,10 @@
; CHECK: t1:
; CHECK: movl 8(%esp), %eax
-; CHECK-NEXT: movl 4(%esp), %ecx
; CHECK-NEXT: movapd (%eax), %xmm0
; CHECK-NEXT: movlpd 12(%esp), %xmm0
-; CHECK-NEXT: movapd %xmm0, (%ecx)
+; CHECK-NEXT: movl 4(%esp), %eax
+; CHECK-NEXT: movapd %xmm0, (%eax)
; CHECK-NEXT: ret
}
@@ -26,9 +26,9 @@
; CHECK: t2:
; CHECK: movl 8(%esp), %eax
-; CHECK-NEXT: movl 4(%esp), %ecx
; CHECK-NEXT: movapd (%eax), %xmm0
; CHECK-NEXT: movhpd 12(%esp), %xmm0
-; CHECK-NEXT: movapd %xmm0, (%ecx)
+; CHECK-NEXT: movl 4(%esp), %eax
+; CHECK-NEXT: movapd %xmm0, (%eax)
; CHECK-NEXT: ret
}
Modified: llvm/trunk/test/CodeGen/X86/sse3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3.ll?rev=98810&r1=98809&r2=98810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse3.ll Thu Mar 18 01:55:42 2010
@@ -17,8 +17,8 @@
; X64: t0:
; X64: movddup (%rsi), %xmm0
-; X64: xorl %eax, %eax
; X64: pshuflw $0, %xmm0, %xmm0
+; X64: xorl %eax, %eax
; X64: pinsrw $0, %eax, %xmm0
; X64: movaps %xmm0, (%rdi)
; X64: ret
@@ -169,11 +169,11 @@
ret void
; X64: t10:
; X64: pextrw $4, %xmm0, %eax
-; X64: pextrw $6, %xmm0, %edx
; X64: movlhps %xmm1, %xmm1
; X64: pshuflw $8, %xmm1, %xmm1
; X64: pinsrw $2, %eax, %xmm1
-; X64: pinsrw $3, %edx, %xmm1
+; X64: pextrw $6, %xmm0, %eax
+; X64: pinsrw $3, %eax, %xmm1
}
@@ -184,8 +184,8 @@
ret <8 x i16> %tmp7
; X64: t11:
-; X64: movlhps %xmm0, %xmm0
; X64: movd %xmm1, %eax
+; X64: movlhps %xmm0, %xmm0
; X64: pshuflw $1, %xmm0, %xmm0
; X64: pinsrw $1, %eax, %xmm0
; X64: ret
@@ -198,8 +198,8 @@
ret <8 x i16> %tmp9
; X64: t12:
-; X64: movlhps %xmm0, %xmm0
; X64: pextrw $3, %xmm1, %eax
+; X64: movlhps %xmm0, %xmm0
; X64: pshufhw $3, %xmm0, %xmm0
; X64: pinsrw $5, %eax, %xmm0
; X64: ret
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