[llvm-commits] [llvm] r97012 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/Thumb2/ldr-str-imm12.ll

[Jim Grosbach]

Author: grosbach
Date: Tue Feb 23 19:43:03 2010
New Revision: 97012

URL: http://llvm.org/viewvc/llvm-project?rev=97012&view=rev
Log:
LowerCall() should always do getCopyFromReg() to reference the stack pointer.
Machine instruction selection is much happier when operands are in virtual
registers.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=97012&r1=97011&r2=97012&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Feb 23 19:43:03 2010
@@ -924,7 +924,7 @@
   // These operations are automatically eliminated by the prolog/epilog pass
   Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
 
-  SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
+  SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
 
   RegsToPassVector RegsToPass;
   SmallVector<SDValue, 8> MemOpChains;
@@ -973,8 +973,6 @@
                            VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
         } else {
           assert(VA.isMemLoc());
-          if (StackPtr.getNode() == 0)
-            StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
 
           MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
                                                  dl, DAG, VA, Flags));
@@ -987,8 +985,6 @@
       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
     } else {
       assert(VA.isMemLoc());
-      if (StackPtr.getNode() == 0)
-        StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
 
       MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
                                              dl, DAG, VA, Flags));

Modified: llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll?rev=97012&r1=97011&r2=97012&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll Tue Feb 23 19:43:03 2010
@@ -52,7 +52,7 @@
 ; CHECK: str r{{[0-7]}}, [sp]
 ; CHECK: str r{{[0-7]}}, [sp, #+4]
 ; CHECK: str r{{[0-7]}}, [sp, #+8]
-; CHECK: str r{{[0-7]}}, [sp, #+24]
+; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #+24]
   store %union.rec* null, %union.rec** @zz_hold, align 4
   store %union.rec* null, %union.rec** @zz_res, align 4
   store %union.rec* %x, %union.rec** @zz_hold, align 4