[llvm-commits] [llvm] r96654 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

[Johnny Chen]

Hi Chris,

These added encodings are are more specific than:

def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
                DPSoRegFrm, IIC_iMOVsr,
                "mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
  let Inst{25} = 0;
}

Relying on the decoder to decode a MOVs super-instruction would mean that
it prints out:

	mov		r0, r0, asr #1

which, according to A8.6.98, is a pseudo-instruction and is not the canonical form we want
for disassembly (A8-199).  And an added bonus is that MOVs cannot handle RRX (A8-282).

Thanks.

On Feb 18, 2010, at 10:06 PM, Chris Lattner wrote:

> 
> On Feb 18, 2010, at 6:12 PM, Johnny Chen wrote:
> 
>> Author: johnny
>> Date: Thu Feb 18 20:12:06 2010
>> New Revision: 96654
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=96654&view=rev
>> Log:
>> Added entries for ASR, LSL, LSR, ROR, and RRX so that the disassembler prints
>> out the canonical form (A8.6.98) instead of the pseudo-instruction as provided
>> via MOVs.
> 
> Hi Johnny,
> 
> Is this a case where this encoding turns into either a mov with asr operand (the canonical form) or into an asr pseudo op which prints better?  If so, it would be better to handle this in the asmprinter than adding redundant encodings for this.  You can see similar examples in the PPC backend.  Please let me know if you need more pointers,
> 
> -Chris
> 
> 
>> 
>> DBG_ARM_DISASM=YES llvm-mc -triple=arm-unknown-unknown --disassemble
>> 0xc0 0x00 0xa0 0xe1
>> Opcode=29 Name=ASR Format=ARM_FORMAT_LDMISCFRM
>> 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
>> -------------------------------------------------------------------------------------------------
>> | 1: 1: 1: 0| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 0: 0: 0|
>> -------------------------------------------------------------------------------------------------
>> 
>> 	asr	r0, r0, #1
>> 
>> Modified:
>>   llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=96654&r1=96653&r2=96654&view=diff
>> 
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Feb 18 20:12:06 2010
>> @@ -1278,6 +1278,30 @@
>>                 "mov", "\t$dst, $src, rrx",
>>                 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
>> 
>> +//===----------------------------------------------------------------------===//
>> +//  Shift Instructions.
>> +//
>> +//  These are for disassembly only.  See also MOVs above.
>> +
>> +class AShI<string opc, bits<2> type>
>> +  : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src, am3offset:$offset), LdMiscFrm,
>> +         IIC_iMOVsr, opc, "\t$dst, $src, $offset", []>, UnaryDP {
>> +  let Inst{6-5} = type;
>> +  let Inst{25} = 0;
>> +}
>> +
>> +def LSL : AShI<"lsl", 0b00>;
>> +def LSR : AShI<"lsr", 0b01>;
>> +def ASR : AShI<"asr", 0b10>;
>> +def ROR : AShI<"ror", 0b11>;
>> +
>> +def RRX : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), LdMiscFrm, IIC_iMOVsr,
>> +               "rrx", "\t$dst, $src", []>, UnaryDP {
>> +  let Inst{25} = 0;
>> +  let Inst{11-7} = 0b00000;
>> +  let Inst{6-4} = 0b110;
>> +}
>> +
>> // These aren't really mov instructions, but we have to define them this way
>> // due to flag operands.
>> 
>> 
>> 
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