[llvm-commits] [llvm] r96640 - in /llvm/trunk: lib/CodeGen/SelectionDAG/TargetLowering.cpp test/CodeGen/X86/xor-icmp.ll

[Evan Cheng]

Author: evancheng
Date: Thu Feb 18 18:34:39 2010
New Revision: 96640

URL: http://llvm.org/viewvc/llvm-project?rev=96640&view=rev
Log:
Transform (xor (setcc), (setcc)) == / != 1 to
(xor (setcc), (setcc)) != / == 1.

e.g. On x86_64
  %0 = icmp eq i32 %x, 0
  %1 = icmp eq i32 %y, 0
  %2 = xor i1 %1, %0
  br i1 %2, label %bb, label %return
=>
	testl   %edi, %edi
	sete    %al
	testl   %esi, %esi
	sete    %cl
	cmpb    %al, %cl
	je      LBB1_2

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    llvm/trunk/test/CodeGen/X86/xor-icmp.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=96640&r1=96639&r2=96640&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Feb 18 18:34:39 2010
@@ -1855,9 +1855,19 @@
         SDValue Op0 = N0;
         if (Op0.getOpcode() == ISD::TRUNCATE)
           Op0 = Op0.getOperand(0);
-        if (Op0.getOpcode() == ISD::AND &&
-            isa<ConstantSDNode>(Op0.getOperand(1)) &&
-            cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
+
+        if ((Op0.getOpcode() == ISD::XOR || Op0.getOpcode() == ISD::AND) &&
+            Op0.getOperand(0).getOpcode() == ISD::SETCC &&
+            Op0.getOperand(1).getOpcode() == ISD::SETCC) {
+          // (and (setcc), (setcc)) == / != 1 -> (setcc) == / != (setcc)
+          // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
+          if (Op0.getOpcode() == ISD::XOR)
+            Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
+          return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
+                              Cond);
+        } else if (Op0.getOpcode() == ISD::AND &&
+                isa<ConstantSDNode>(Op0.getOperand(1)) &&
+                cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
           if (Op0.getValueType() != VT)
             Op0 = DAG.getNode(ISD::AND, dl, VT,
                           DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),

Modified: llvm/trunk/test/CodeGen/X86/xor-icmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/xor-icmp.ll?rev=96640&r1=96639&r2=96640&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/xor-icmp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/xor-icmp.ll Thu Feb 18 18:34:39 2010
@@ -1,5 +1,6 @@
 ; RUN: llc < %s -march=x86    | FileCheck %s -check-prefix=X32
 ; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=X64
+; rdar://7367229
 
 define i32 @t(i32 %a, i32 %b) nounwind ssp {
 entry:
@@ -34,3 +35,33 @@
 declare i32 @foo(...)
 
 declare i32 @bar(...)
+
+define i32 @t2(i32 %x, i32 %y) nounwind ssp {
+; X32: t2:
+; X32: cmpl
+; X32: sete
+; X32: cmpl
+; X32: sete
+; X32-NOT: xor
+; X32: je
+
+; X64: t2:
+; X64: testl
+; X64: sete
+; X64: testl
+; X64: sete
+; X64-NOT: xor
+; X64: je
+entry:
+  %0 = icmp eq i32 %x, 0                          ; <i1> [#uses=1]
+  %1 = icmp eq i32 %y, 0                          ; <i1> [#uses=1]
+  %2 = xor i1 %1, %0                              ; <i1> [#uses=1]
+  br i1 %2, label %bb, label %return
+
+bb:                                               ; preds = %entry
+  %3 = tail call i32 (...)* @foo() nounwind       ; <i32> [#uses=0]
+  ret i32 undef
+
+return:                                           ; preds = %entry
+  ret i32 undef
+}