[llvm-commits] [llvm] r95548 - /llvm/trunk/lib/Target/ARM/ARMInstrVFP.td

[Johnny Chen]

Author: johnny
Date: Mon Feb  8 11:26:09 2010
New Revision: 95548

URL: http://llvm.org/viewvc/llvm-project?rev=95548&view=rev
Log:
Added VMOVRRS/VMOVSRR to ARMInstrVFP.td for disassembly purpose.

A8.6.331 VMOV (between two ARM core registers and two single-precision registers)

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrVFP.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=95548&r1=95547&r2=95548&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Mon Feb  8 11:26:09 2010
@@ -252,6 +252,13 @@
   let Inst{7-6} = 0b00;
 }
 
+def VMOVRRS  : AVConv3I<0b11000101, 0b1010,
+                      (outs GPR:$wb, GPR:$dst2), (ins SPR:$src1, SPR:$src2),
+                 IIC_VMOVDI, "vmov", "\t$wb, $dst2, $src1, $src2",
+                 [/* For disassembly only; pattern left blank */]> {
+  let Inst{7-6} = 0b00;
+}
+
 // FMDHR: GPR -> SPR
 // FMDLR: GPR -> SPR
 
@@ -262,6 +269,13 @@
   let Inst{7-6} = 0b00;
 }
 
+def VMOVSRR : AVConv5I<0b11000100, 0b1010,
+                     (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
+                IIC_VMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
+                [/* For disassembly only; pattern left blank */]> {
+  let Inst{7-6} = 0b00;
+}
+
 // FMRDH: SPR -> GPR
 // FMRDL: SPR -> GPR
 // FMRRS: SPR -> GPR