[llvm-commits] [llvm] r93829 - in /llvm/trunk/lib/Target/ARM: ARMISelDAGToDAG.cpp ARMInstrInfo.td ARMInstrThumb2.td

[Evan Cheng]

Author: evancheng
Date: Mon Jan 18 18:44:15 2010
New Revision: 93829

URL: http://llvm.org/viewvc/llvm-project?rev=93829&view=rev
Log:
Fix r93758. Use isel patterns instead of c++ selection code to select rbit and make sure we pick different instructions for ARM vs. Thumb2.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=93829&r1=93828&r2=93829&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Jan 18 18:44:15 2010
@@ -1680,12 +1680,6 @@
     return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
                                   N->getOperand(0), getAL(CurDAG),
                                   CurDAG->getRegister(0, MVT::i32));
-  case ARMISD::RBIT: {
-    EVT VT = N->getValueType(0);
-    SDValue Ops[] = { N->getOperand(0),
-                      getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
-    return CurDAG->getMachineNode(ARM::RBIT, dl, VT, Ops, 3);
-  }
   case ISD::UMUL_LOHI: {
     if (Subtarget->isThumb1Only())
       break;

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=93829&r1=93828&r2=93829&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Jan 18 18:44:15 2010
@@ -107,6 +107,8 @@
 def ARMSyncBarrierV6 : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIERV6,
                               [SDNPHasChain]>;
 
+def ARMrbit          : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
+
 //===----------------------------------------------------------------------===//
 // ARM Instruction Predicate Definitions.
 //
@@ -1456,7 +1458,9 @@
 }
 
 def RBIT : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
-              "rbit", "\t$dst, $src", []>, Requires<[IsARM, HasV6T2]> {
+              "rbit", "\t$dst, $src",
+              [(set GPR:$dst, (ARMrbit GPR:$src))]>,
+           Requires<[IsARM, HasV6T2]> {
   let Inst{7-4}   = 0b0011;
   let Inst{11-8}  = 0b1111;
   let Inst{19-16} = 0b1111;

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=93829&r1=93828&r2=93829&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Jan 18 18:44:15 2010
@@ -1541,7 +1541,8 @@
                     "clz", "\t$dst, $src", [(set GPR:$dst, (ctlz GPR:$src))]>;
 
 def t2RBIT : T2I_misc<0b01, 0b10, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
-                      "rbit", "\t$dst, $src", []>;
+                      "rbit", "\t$dst, $src",
+                      [(set GPR:$dst, (ARMrbit GPR:$src))]>;
 
 def t2REV : T2I_misc<0b01, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
                    "rev", ".w\t$dst, $src", [(set GPR:$dst, (bswap GPR:$src))]>;