[llvm-commits] [llvm] r93677 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td test/CodeGen/ARM/vbits.ll

[Bob Wilson]

Author: bwilson
Date: Sun Jan 17 00:35:17 2010
New Revision: 93677

URL: http://llvm.org/viewvc/llvm-project?rev=93677&view=rev
Log:
The Neon "vtst" instruction takes a suffix that is the element size alone --
adding an "i" to the suffix, indicating that the elements are integers, is
accepted but not part of the standard syntax.  This helps us pass a few more
of the Neon tests from gcc.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/CodeGen/ARM/vbits.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=93677&r1=93676&r2=93677&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Sun Jan 17 00:35:17 2010
@@ -2116,7 +2116,7 @@
                         v4i32, v4f32, int_arm_neon_vacgtq, 0>;
 //   VTST     : Vector Test Bits
 defm VTST     : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 
-                        IIC_VBINi4Q, "vtst", "i", NEONvtst, 1>;
+                        IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
 
 // Vector Bitwise Operations.
 

Modified: llvm/trunk/test/CodeGen/ARM/vbits.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vbits.ll?rev=93677&r1=93676&r2=93677&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vbits.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vbits.ll Sun Jan 17 00:35:17 2010
@@ -442,7 +442,7 @@
 
 define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK: vtsti8:
-;CHECK: vtst.i8
+;CHECK: vtst.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
 	%tmp3 = and <8 x i8> %tmp1, %tmp2
@@ -453,7 +453,7 @@
 
 define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK: vtsti16:
-;CHECK: vtst.i16
+;CHECK: vtst.16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
 	%tmp3 = and <4 x i16> %tmp1, %tmp2
@@ -464,7 +464,7 @@
 
 define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK: vtsti32:
-;CHECK: vtst.i32
+;CHECK: vtst.32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
 	%tmp3 = and <2 x i32> %tmp1, %tmp2
@@ -475,7 +475,7 @@
 
 define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK: vtstQi8:
-;CHECK: vtst.i8
+;CHECK: vtst.8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
 	%tmp3 = and <16 x i8> %tmp1, %tmp2
@@ -486,7 +486,7 @@
 
 define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK: vtstQi16:
-;CHECK: vtst.i16
+;CHECK: vtst.16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
 	%tmp3 = and <8 x i16> %tmp1, %tmp2
@@ -497,7 +497,7 @@
 
 define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK: vtstQi32:
-;CHECK: vtst.i32
+;CHECK: vtst.32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
 	%tmp3 = and <4 x i32> %tmp1, %tmp2