[llvm-commits] [llvm] r93204 - in /llvm/trunk: lib/Target/X86/X86FastISel.cpp test/CodeGen/X86/fast-isel.ll

[Evan Cheng]

Author: evancheng
Date: Mon Jan 11 16:59:27 2010
New Revision: 93204

URL: http://llvm.org/viewvc/llvm-project?rev=93204&view=rev
Log:
Add manual ISD::OR fastisel selection routines. TableGen is no longer autogen them after 93152 and 93191.

Modified:
    llvm/trunk/lib/Target/X86/X86FastISel.cpp
    llvm/trunk/test/CodeGen/X86/fast-isel.ll

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=93204&r1=93203&r2=93204&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Mon Jan 11 16:59:27 2010
@@ -104,6 +104,8 @@
 
   bool X86SelectBranch(Instruction *I);
 
+  bool X86SelectOR(Instruction *I);
+
   bool X86SelectShift(Instruction *I);
 
   bool X86SelectSelect(Instruction *I);
@@ -945,6 +947,44 @@
   return true;
 }
 
+bool X86FastISel::X86SelectOR(Instruction *I) {
+  // FIXME: This is necessary because tablegen stopped generate fastisel
+  // patterns after 93152 and 93191 (which turns OR to ADD if the set
+  // bits in the source operands are known not to overlap).
+  const TargetRegisterClass *RC = NULL;
+  unsigned OpReg = 0, OpImm = 0;
+  if (I->getType()->isInteger(16)) {
+    RC = X86::GR16RegisterClass;
+    OpReg = X86::OR16rr; OpImm = X86::OR16ri;
+  } else if (I->getType()->isInteger(32)) {
+    RC = X86::GR32RegisterClass;
+    OpReg = X86::OR32rr; OpImm = X86::OR32ri;
+  } else if (I->getType()->isInteger(64)) {
+    RC = X86::GR64RegisterClass;
+    OpReg = X86::OR32rr; OpImm = X86::OR32ri;
+  } else
+    return false;
+
+  unsigned Op0Reg = getRegForValue(I->getOperand(0));
+  if (Op0Reg == 0) return false;
+  
+  if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
+    unsigned ResultReg = createResultReg(RC);
+    BuildMI(MBB, DL, TII.get(OpImm), ResultReg).addReg(Op0Reg)
+      .addImm(CI->getZExtValue());
+    UpdateValueMap(I, ResultReg);
+    return true;
+  }
+
+  unsigned Op1Reg = getRegForValue(I->getOperand(1));
+  if (Op1Reg == 0) return false;
+
+  unsigned ResultReg = createResultReg(RC);
+  BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg).addReg(Op1Reg);
+  UpdateValueMap(I, ResultReg);
+  return true;
+}
+
 bool X86FastISel::X86SelectShift(Instruction *I) {
   unsigned CReg = 0, OpReg = 0, OpImm = 0;
   const TargetRegisterClass *RC = NULL;
@@ -1534,6 +1574,8 @@
     return X86SelectBranch(I);
   case Instruction::Call:
     return X86SelectCall(I);
+  case Instruction::Or:
+    return X86SelectOR(I);
   case Instruction::LShr:
   case Instruction::AShr:
   case Instruction::Shl:

Modified: llvm/trunk/test/CodeGen/X86/fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel.ll?rev=93204&r1=93203&r2=93204&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel.ll Mon Jan 11 16:59:27 2010
@@ -14,7 +14,7 @@
   %t1 = mul i32 %t0, %s
   %t2 = sub i32 %t1, %s
   %t3 = and i32 %t2, %s
-  %t4 = xor i32 %t3, 3
+  %t4 = or i32 %t3, %s
   %t5 = xor i32 %t4, %s
   %t6 = add i32 %t5, 2
   %t7 = getelementptr i32* %y, i32 1