[llvm-commits] [llvm] r91944 - in /llvm/trunk/lib/Target/ARM: ARMInstrThumb.td ARMRegisterInfo.td

[Jakob Stoklund Olesen]

On Dec 22, 2009, at 4:01 PM, Chris Lattner wrote:

> 
> On Dec 22, 2009, at 3:54 PM, Jakob Stoklund Olesen wrote:
> 
>> Author: stoklund
>> Date: Tue Dec 22 17:54:44 2009
>> New Revision: 91944
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=91944&view=rev
>> Log:
>> Add a SPR register class to the ARM target.
>> 
>> Certain Thumb instructions require only SP (e.g. tSTRspi).
> 
> Hi Jakob,
> 
> If it only allows one register, doesn't it make more sense to make it an implicit reg operand instead of a regclass operand?

Maybe. How would it look in this pattern?

def t_addrmode_sp : Operand<i32>,
                    ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
  let PrintMethod = "printThumbAddrModeSPOperand";
  let MIOperandInfo = (ops JustSP:$base, i32imm:$offsimm);
}

let canFoldAsLoad = 1 in
def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
                  "ldr", "\t$dst, $addr",
                  [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>,
              T1LdStSP<{1,?,?}>;

There is some magic in ARMDAGToDAGISel::SelectThumbAddrModeRI5 to make the pattern match. I would think that only eliminateFrameIndex() would be interested in SP-relative addressing, but I am not completely sure what is going on.

I was trying to break as little as possible.

/jakob