[llvm-commits] [llvm] r91378 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/setcc.ll test/CodeGen/X86/zext-shl.ll

[Eli Friedman]

On Mon, Dec 14, 2009 at 4:41 PM, Evan Cheng <evan.cheng at apple.com> wrote:
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Dec 14 18:41:36 2009
> @@ -3278,6 +3278,16 @@
>     if (SCC.getNode()) return SCC;
>   }
>
> +  // (zext (shl (zext x), y)) -> (shl (zext x), (zext y))
> +  if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
> +      N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
> +      N0.hasOneUse()) {
> +    DebugLoc dl = N->getDebugLoc();
> +    return DAG.getNode(N0.getOpcode(), dl, VT,
> +                       DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)),
> +                       DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(1)));
> +  }
> +
>   return SDValue();
>  }

I think you need a check here to make sure the original shift never
shifts out any set bits.  (Only happens with unusual widths, but I
think it's possible before legalization.)

-Eli