[llvm-commits] [llvm] r91158 - in /llvm/trunk: include/llvm/CodeGen/ValueTypes.h lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

Villmow, Micah Micah.Villmow at amd.com
Mon Dec 14 13:10:43 PST 2009


Dan,
 I've applied this patch set and it still does not work correctly. The
problem seems to be an assert in TargetLowering.cpp.
assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth
> &&
>           "Mask size mismatches value type size!");

This occurs on a truncating store of a vector type. I've attached the
test case that I am using to get past this. The problem seems to be that
the BitWidth of the mask is the vector bitwidth and not the scalar
bitwidth.

This test case asserts on both my backend and x86.

> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-
> bounces at cs.uiuc.edu] On Behalf Of Dan Gohman
> Sent: Friday, December 11, 2009 1:31 PM
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm-commits] [llvm] r91158 - in /llvm/trunk:
> include/llvm/CodeGen/ValueTypes.h
> lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> lib/CodeGen/SelectionDAG/LegalizeTypes.h
> lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp lib/
> 
> Author: djg
> Date: Fri Dec 11 15:31:27 2009
> New Revision: 91158
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=91158&view=rev
> Log:
> Implement vector widening, splitting, and scalarizing for
> SIGN_EXTEND_INREG.
> 
> Added:
>     llvm/trunk/test/CodeGen/X86/vec_ext_inreg.ll
> Modified:
>     llvm/trunk/include/llvm/CodeGen/ValueTypes.h
>     llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>     llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>     llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
>     llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
>     llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
>     llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>     llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
>     llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> 
> Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h
> URL: http://llvm.org/viewvc/llvm-
>
project/llvm/trunk/include/llvm/CodeGen/ValueTypes.h?rev=91158&r1=91157
> &r2=91158&view=diff
> 
>
=======================================================================
> =======
> --- llvm/trunk/include/llvm/CodeGen/ValueTypes.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/ValueTypes.h Fri Dec 11 15:31:27
> 2009
> @@ -166,6 +166,12 @@
>          return *this;
>        }
>      }
> +
> +    /// getScalarType - If this is a vector type, return the element
> type,
> +    /// otherwise return this.
> +    MVT getScalarType() const {
> +      return isVector() ? getVectorElementType() : *this;
> +    }
> 
>      MVT getVectorElementType() const {
>        switch (SimpleTy) {
> @@ -524,6 +530,12 @@
>        return V;
>      }
> 
> +    /// getScalarType - If this is a vector type, return the element
> type,
> +    /// otherwise return this.
> +    EVT getScalarType() const {
> +      return isVector() ? getVectorElementType() : *this;
> +    }
> +
>      /// getVectorElementType - Given a vector type, return the type
of
>      /// each element.
>      EVT getVectorElementType() const {
> 
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: http://llvm.org/viewvc/llvm-
>
project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=91158&r
> 1=91157&r2=91158&view=diff
> 
>
=======================================================================
> =======
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Dec 11
> 15:31:27 2009
> @@ -119,7 +119,8 @@
>      /// it can be simplified or if things it uses can be simplified
by
> bit
>      /// propagation.  If so, return true.
>      bool SimplifyDemandedBits(SDValue Op) {
> -      APInt Demanded =
> APInt::getAllOnesValue(Op.getValueSizeInBits());
> +      unsigned BitWidth =
> Op.getValueType().getScalarType().getSizeInBits();
> +      APInt Demanded = APInt::getAllOnesValue(BitWidth);
>        return SimplifyDemandedBits(Op, Demanded);
>      }
> 
> @@ -2441,7 +2442,7 @@
>    ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
>    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
>    EVT VT = N0.getValueType();
> -  unsigned OpSizeInBits = VT.getSizeInBits();
> +  unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
> 
>    // fold (shl c1, c2) -> c1<<c2
>    if (N0C && N1C)
> @@ -2457,7 +2458,7 @@
>      return N0;
>    // if (shl x, c) is known to be zero, return 0
>    if (DAG.MaskedValueIsZero(SDValue(N, 0),
> -
> APInt::getAllOnesValue(VT.getSizeInBits())))
> +                            APInt::getAllOnesValue(OpSizeInBits)))
>      return DAG.getConstant(0, VT);
>    // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y),
> (trunc c))).
>    if (N1.getOpcode() == ISD::TRUNCATE &&
> @@ -2533,6 +2534,7 @@
>    ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
>    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
>    EVT VT = N0.getValueType();
> +  unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
> 
>    // fold (sra c1, c2) -> (sra c1, c2)
>    if (N0C && N1C)
> @@ -2544,7 +2546,7 @@
>    if (N0C && N0C->isAllOnesValue())
>      return N0;
>    // fold (sra x, (setge c, size(x))) -> undef
> -  if (N1C && N1C->getZExtValue() >= VT.getSizeInBits())
> +  if (N1C && N1C->getZExtValue() >= OpSizeInBits)
>      return DAG.getUNDEF(VT);
>    // fold (sra x, 0) -> x
>    if (N1C && N1C->isNullValue())
> @@ -2552,7 +2554,7 @@
>    // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target
> supports
>    // sext_inreg.
>    if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
> -    unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C-
> >getZExtValue();
> +    unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
>      EVT EVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
>      if ((!LegalOperations ||
> TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)))
>        return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
VT,
> @@ -2563,7 +2565,7 @@
>    if (N1C && N0.getOpcode() == ISD::SRA) {
>      if (ConstantSDNode *C1 =
> dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
>        unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
> -      if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1;
> +      if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
>        return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
> N0.getOperand(0),
>                           DAG.getConstant(Sum, N1C->getValueType(0)));
>      }
> @@ -2579,9 +2581,8 @@
>      const ConstantSDNode *N01C =
> dyn_cast<ConstantSDNode>(N0.getOperand(1));
>      if (N01C && N1C) {
>        // Determine what the truncate's result bitsize and type would
> be.
> -      unsigned VTValSize = VT.getSizeInBits();
>        EVT TruncVT =
> -        EVT::getIntegerVT(*DAG.getContext(), VTValSize - N1C-
> >getZExtValue());
> +        EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C-
> >getZExtValue());
>        // Determine the residual right-shift amount.
>        signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
> 
> @@ -2614,7 +2615,7 @@
>        EVT TruncVT = N1.getValueType();
>        SDValue N100 = N1.getOperand(0).getOperand(0);
>        APInt TruncC = N101C->getAPIntValue();
> -      TruncC.trunc(TruncVT.getSizeInBits());
> +      TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
>        return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
>                           DAG.getNode(ISD::AND, N->getDebugLoc(),
>                                       TruncVT,
> @@ -2643,7 +2644,7 @@
>    ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
>    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
>    EVT VT = N0.getValueType();
> -  unsigned OpSizeInBits = VT.getSizeInBits();
> +  unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
> 
>    // fold (srl c1, c2) -> c1 >>u c2
>    if (N0C && N1C)
> @@ -3036,7 +3037,7 @@
>        else if (Op.getValueType().bitsGT(VT))
>          Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
>        return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
VT,
> Op,
> -                         DAG.getValueType(N0.getValueType()));
> +
> DAG.getValueType(N0.getValueType().getScalarType()));
>      }
>    }
> 
> @@ -3177,7 +3178,8 @@
>      } else if (Op.getValueType().bitsGT(VT)) {
>        Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
>      }
> -    return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
> N0.getValueType());
> +    return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
> +                                  N0.getValueType().getScalarType());
>    }
> 
>    // Fold (zext (and (trunc x), cst)) -> (and x, cst),
> @@ -3536,7 +3538,7 @@
>    SDValue N1 = N->getOperand(1);
>    EVT VT = N->getValueType(0);
>    EVT EVT = cast<VTSDNode>(N1)->getVT();
> -  unsigned VTBits = VT.getSizeInBits();
> +  unsigned VTBits = VT.getScalarType().getSizeInBits();
>    unsigned EVTBits = EVT.getSizeInBits();
> 
>    // fold (sext_in_reg c1) -> c1
> @@ -3544,7 +3546,7 @@
>      return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
> N0, N1);
> 
>    // If the input is already sign extended, just drop the extension.
> -  if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1)
> +  if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
>      return N0;
> 
>    // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x,
> minVT) pt2
> @@ -3559,7 +3561,7 @@
>    // if x is small enough.
>    if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() ==
> ISD::ANY_EXTEND) {
>      SDValue N00 = N0.getOperand(0);
> -    if (N00.getValueType().getSizeInBits() < EVTBits)
> +    if (N00.getValueType().getScalarType().getSizeInBits() < EVTBits)
>        return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00,
> N1);
>    }
> 
> @@ -3583,11 +3585,11 @@
>    // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25"
> above.
>    if (N0.getOpcode() == ISD::SRL) {
>      if (ConstantSDNode *ShAmt =
> dyn_cast<ConstantSDNode>(N0.getOperand(1)))
> -      if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) {
> +      if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
>          // We can turn this into an SRA iff the input to the SRL is
> already sign
>          // extended enough.
>          unsigned InSignBits =
> DAG.ComputeNumSignBits(N0.getOperand(0));
> -        if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) <
> InSignBits)
> +        if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
>            return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
>                               N0.getOperand(0), N0.getOperand(1));
>        }
> 
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> URL: http://llvm.org/viewvc/llvm-
>
project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=91158&r
> 1=91157&r2=91158&view=diff
> 
>
=======================================================================
> =======
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Dec 11
> 15:31:27 2009
> @@ -2294,9 +2294,16 @@
>      // NOTE: we could fall back on load/store here too for targets
> without
>      // SAR.  However, it is doubtful that any exist.
>      EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
> -    unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
> +    EVT VT = Node->getValueType(0);
> +    EVT ShiftAmountTy = TLI.getShiftAmountTy();
> +    if (ExtraVT.isVector()) ExtraVT = ExtraVT.getVectorElementType();
> +    if (VT.isVector()) {
> +      ShiftAmountTy = VT;
> +      VT = VT.getVectorElementType();
> +    }
> +    unsigned BitsDiff = VT.getSizeInBits() -
>                          ExtraVT.getSizeInBits();
> -    SDValue ShiftCst = DAG.getConstant(BitsDiff,
> TLI.getShiftAmountTy());
> +    SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
>      Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
>                         Node->getOperand(0), ShiftCst);
>      Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1,
> ShiftCst);
> 
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
> URL: http://llvm.org/viewvc/llvm-
>
project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=91158&r
> 1=91157&r2=91158&view=diff
> 
>
=======================================================================
> =======
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Fri Dec 11
> 15:31:27 2009
> @@ -517,6 +517,7 @@
>    SDValue ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N);
>    SDValue ScalarizeVecRes_LOAD(LoadSDNode *N);
>    SDValue ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N);
> +  SDValue ScalarizeVecRes_SIGN_EXTEND_INREG(SDNode *N);
>    SDValue ScalarizeVecRes_SELECT(SDNode *N);
>    SDValue ScalarizeVecRes_SELECT_CC(SDNode *N);
>    SDValue ScalarizeVecRes_SETCC(SDNode *N);
> @@ -560,6 +561,7 @@
>    void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue
> &Hi);
>    void SplitVecRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi);
>    void SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, SDValue
> &Hi);
> +  void SplitVecRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue
> &Hi);
>    void SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
>    void SplitVecRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi);
>    void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue
&Lo,
> @@ -602,6 +604,7 @@
>    SDValue WidenVecRes_INSERT_VECTOR_ELT(SDNode* N);
>    SDValue WidenVecRes_LOAD(SDNode* N);
>    SDValue WidenVecRes_SCALAR_TO_VECTOR(SDNode* N);
> +  SDValue WidenVecRes_SIGN_EXTEND_INREG(SDNode* N);
>    SDValue WidenVecRes_SELECT(SDNode* N);
>    SDValue WidenVecRes_SELECT_CC(SDNode* N);
>    SDValue WidenVecRes_UNDEF(SDNode *N);
> 
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
> URL: http://llvm.org/viewvc/llvm-
>
project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp?rev=9
> 1158&r1=91157&r2=91158&view=diff
> 
>
=======================================================================
> =======
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp Fri Dec
> 11 15:31:27 2009
> @@ -179,6 +179,7 @@
>    case ISD::FRINT:
>    case ISD::FNEARBYINT:
>    case ISD::FFLOOR:
> +  case ISD::SIGN_EXTEND_INREG:
>      QueryType = Node->getValueType(0);
>      break;
>    case ISD::SINT_TO_FP:
> 
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
> URL: http://llvm.org/viewvc/llvm-
>
project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev
> =91158&r1=91157&r2=91158&view=diff
> 
>
=======================================================================
> =======
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Fri
Dec
> 11 15:31:27 2009
> @@ -54,6 +54,7 @@
>    case ISD::INSERT_VECTOR_ELT: R =
> ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
>    case ISD::LOAD:           R =
> ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
>    case ISD::SCALAR_TO_VECTOR:  R =
> ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
> +  case ISD::SIGN_EXTEND_INREG: R =
> ScalarizeVecRes_SIGN_EXTEND_INREG(N); break;
>    case ISD::SELECT:            R = ScalarizeVecRes_SELECT(N); break;
>    case ISD::SELECT_CC:         R = ScalarizeVecRes_SELECT_CC(N);
> break;
>    case ISD::SETCC:             R = ScalarizeVecRes_SETCC(N); break;
> @@ -195,6 +196,13 @@
>    return InOp;
>  }
> 
> +SDValue DAGTypeLegalizer::ScalarizeVecRes_SIGN_EXTEND_INREG(SDNode
*N)
> {
> +  EVT EltVT = N->getValueType(0).getVectorElementType();
> +  SDValue LHS = GetScalarizedVector(N->getOperand(0));
> +  return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), EltVT,
> +                     LHS, N->getOperand(1));
> +}
> +
>  SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
>    SDValue LHS = GetScalarizedVector(N->getOperand(1));
>    return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
> @@ -401,6 +409,7 @@
>    case ISD::FPOWI:             SplitVecRes_FPOWI(N, Lo, Hi); break;
>    case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo,
> Hi); break;
>    case ISD::SCALAR_TO_VECTOR:  SplitVecRes_SCALAR_TO_VECTOR(N, Lo,
> Hi); break;
> +  case ISD::SIGN_EXTEND_INREG: SplitVecRes_SIGN_EXTEND_INREG(N, Lo,
> Hi); break;
>    case ISD::LOAD:
>      SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
>      break;
> @@ -700,6 +709,18 @@
>    Hi = DAG.getUNDEF(HiVT);
>  }
> 
> +void DAGTypeLegalizer::SplitVecRes_SIGN_EXTEND_INREG(SDNode *N,
> SDValue &Lo,
> +                                                     SDValue &Hi) {
> +  SDValue LHSLo, LHSHi;
> +  GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
> +  DebugLoc dl = N->getDebugLoc();
> +
> +  Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
> +                   N->getOperand(1));
> +  Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
> +                   N->getOperand(1));
> +}
> +
>  void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
>                                          SDValue &Hi) {
>    assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type
> legalization!");
> @@ -1141,6 +1162,7 @@
>    case ISD::INSERT_VECTOR_ELT: Res =
WidenVecRes_INSERT_VECTOR_ELT(N);
> break;
>    case ISD::LOAD:              Res = WidenVecRes_LOAD(N); break;
>    case ISD::SCALAR_TO_VECTOR:  Res = WidenVecRes_SCALAR_TO_VECTOR(N);
> break;
> +  case ISD::SIGN_EXTEND_INREG: Res =
WidenVecRes_SIGN_EXTEND_INREG(N);
> break;
>    case ISD::SELECT:            Res = WidenVecRes_SELECT(N); break;
>    case ISD::SELECT_CC:         Res = WidenVecRes_SELECT_CC(N); break;
>    case ISD::UNDEF:             Res = WidenVecRes_UNDEF(N); break;
> @@ -1691,6 +1713,13 @@
>                       WidenVT, N->getOperand(0));
>  }
> 
> +SDValue DAGTypeLegalizer::WidenVecRes_SIGN_EXTEND_INREG(SDNode *N) {
> +  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N-
> >getValueType(0));
> +  SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
> +  return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
> +                     WidenVT, WidenLHS, N->getOperand(1));
> +}
> +
>  SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
>    EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N-
> >getValueType(0));
>    unsigned WidenNumElts = WidenVT.getVectorNumElements();
> 
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> URL: http://llvm.org/viewvc/llvm-
>
project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=91158&
> r1=91157&r2=91158&view=diff
> 
>
=======================================================================
> =======
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Dec 11
> 15:31:27 2009
> @@ -832,8 +832,12 @@
>  }
> 
>  SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, EVT
> VT) {
> +  assert(!VT.isVector() &&
> +         "getZeroExtendInReg should use the vector element type
> instead of "
> +         "the vector type!");
>    if (Op.getValueType() == VT) return Op;
> -  APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(),
> +  unsigned BitWidth =
> Op.getValueType().getScalarType().getSizeInBits();
> +  APInt Imm = APInt::getLowBitsSet(BitWidth,
>                                     VT.getSizeInBits());
>    return getNode(ISD::AND, DL, Op.getValueType(), Op,
>                   getConstant(Imm, Op.getValueType()));
> @@ -1481,7 +1485,7 @@
>    if (Op.getValueType().isVector())
>      return false;
> 
> -  unsigned BitWidth = Op.getValueSizeInBits();
> +  unsigned BitWidth =
> Op.getValueType().getScalarType().getSizeInBits();
>    return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth);
>  }
> 
> @@ -1504,7 +1508,7 @@
>                                       APInt &KnownZero, APInt
> &KnownOne,
>                                       unsigned Depth) const {
>    unsigned BitWidth = Mask.getBitWidth();
> -  assert(BitWidth == Op.getValueType().getSizeInBits() &&
> +  assert(BitWidth ==
Op.getValueType().getScalarType().getSizeInBits()
> &&
>           "Mask size mismatches value type size!");
> 
>    KnownZero = KnownOne = APInt(BitWidth, 0);   // Don't know
anything.
> @@ -1761,7 +1765,7 @@
>    }
>    case ISD::ZERO_EXTEND: {
>      EVT InVT = Op.getOperand(0).getValueType();
> -    unsigned InBits = InVT.getSizeInBits();
> +    unsigned InBits = InVT.getScalarType().getSizeInBits();
>      APInt NewBits   = APInt::getHighBitsSet(BitWidth, BitWidth -
> InBits) & Mask;
>      APInt InMask    = Mask;
>      InMask.trunc(InBits);
> @@ -1775,7 +1779,7 @@
>    }
>    case ISD::SIGN_EXTEND: {
>      EVT InVT = Op.getOperand(0).getValueType();
> -    unsigned InBits = InVT.getSizeInBits();
> +    unsigned InBits = InVT.getScalarType().getSizeInBits();
>      APInt InSignBit = APInt::getSignBit(InBits);
>      APInt NewBits   = APInt::getHighBitsSet(BitWidth, BitWidth -
> InBits) & Mask;
>      APInt InMask = Mask;
> @@ -1816,7 +1820,7 @@
>    }
>    case ISD::ANY_EXTEND: {
>      EVT InVT = Op.getOperand(0).getValueType();
> -    unsigned InBits = InVT.getSizeInBits();
> +    unsigned InBits = InVT.getScalarType().getSizeInBits();
>      APInt InMask = Mask;
>      InMask.trunc(InBits);
>      KnownZero.trunc(InBits);
> @@ -1828,7 +1832,7 @@
>    }
>    case ISD::TRUNCATE: {
>      EVT InVT = Op.getOperand(0).getValueType();
> -    unsigned InBits = InVT.getSizeInBits();
> +    unsigned InBits = InVT.getScalarType().getSizeInBits();
>      APInt InMask = Mask;
>      InMask.zext(InBits);
>      KnownZero.zext(InBits);
> @@ -1961,7 +1965,7 @@
>  unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth)
> const{
>    EVT VT = Op.getValueType();
>    assert(VT.isInteger() && "Invalid VT!");
> -  unsigned VTBits = VT.getSizeInBits();
> +  unsigned VTBits = VT.getScalarType().getSizeInBits();
>    unsigned Tmp, Tmp2;
>    unsigned FirstAnswer = 1;
> 
> @@ -1988,7 +1992,7 @@
>    }
> 
>    case ISD::SIGN_EXTEND:
> -    Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits();
> +    Tmp = VTBits-
> Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
>      return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp;
> 
>    case ISD::SIGN_EXTEND_INREG:
> @@ -2624,6 +2628,9 @@
>      assert(VT == N1.getValueType() && "Not an inreg extend!");
>      assert(VT.isInteger() && EVT.isInteger() &&
>             "Cannot *_EXTEND_INREG FP types");
> +    assert(!EVT.isVector() &&
> +           "AssertSExt/AssertZExt type should be the vector element
> type "
> +           "rather than the vector type!");
>      assert(EVT.bitsLE(VT) && "Not extending!");
>      if (VT == EVT) return N1; // noop assertion.
>      break;
> @@ -2633,12 +2640,15 @@
>      assert(VT == N1.getValueType() && "Not an inreg extend!");
>      assert(VT.isInteger() && EVT.isInteger() &&
>             "Cannot *_EXTEND_INREG FP types");
> -    assert(EVT.bitsLE(VT) && "Not extending!");
> +    assert(!EVT.isVector() &&
> +           "SIGN_EXTEND_INREG type should be the vector element type
> rather "
> +           "than the vector type!");
> +    assert(EVT.bitsLE(VT.getScalarType()) && "Not extending!");
>      if (EVT == VT) return N1;  // Not actually extending
> 
>      if (N1C) {
>        APInt Val = N1C->getAPIntValue();
> -      unsigned FromBits =
cast<VTSDNode>(N2)->getVT().getSizeInBits();
> +      unsigned FromBits = EVT.getSizeInBits();
>        Val <<= Val.getBitWidth()-FromBits;
>        Val = Val.ashr(Val.getBitWidth()-FromBits);
>        return getConstant(Val, VT);
> 
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> URL: http://llvm.org/viewvc/llvm-
>
project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=9115
> 8&r1=91157&r2=91158&view=diff
> 
>
=======================================================================
> =======
> --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Fri Dec 11
> 15:31:27 2009
> @@ -911,7 +911,7 @@
>                                            TargetLoweringOpt &TLO,
>                                            unsigned Depth) const {
>    unsigned BitWidth = DemandedMask.getBitWidth();
> -  assert(Op.getValueSizeInBits() == BitWidth &&
> +  assert(Op.getValueType().getScalarType().getSizeInBits() ==
BitWidth
> &&
>           "Mask size mismatches value type size!");
>    APInt NewMask = DemandedMask;
>    DebugLoc dl = Op.getDebugLoc();
> @@ -1240,7 +1240,7 @@
>        // demand the input sign bit.
>        APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
>        if (HighBits.intersects(NewMask))
> -        InDemandedMask |= APInt::getSignBit(VT.getSizeInBits());
> +        InDemandedMask |=
> APInt::getSignBit(VT.getScalarType().getSizeInBits());
> 
>        if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
>                                 KnownZero, KnownOne, TLO, Depth+1))
> 
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-
>
project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=91158&r1=9115
> 7&r2=91158&view=diff
> 
>
=======================================================================
> =======
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Dec 11 15:31:27
> 2009
> @@ -595,6 +595,7 @@
>      setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT,
> Expand);
>      setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT,
> Expand);
>      setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT,
> Expand);
> +    setOperationAction(ISD::SIGN_EXTEND_INREG,
> (MVT::SimpleValueType)VT,Expand);
>    }
> 
>    // FIXME: In order to prevent SSE instructions being expanded to
MMX
> ones
> 
> Added: llvm/trunk/test/CodeGen/X86/vec_ext_inreg.ll
> URL: http://llvm.org/viewvc/llvm-
>
project/llvm/trunk/test/CodeGen/X86/vec_ext_inreg.ll?rev=91158&view=aut
> o
> 
>
=======================================================================
> =======
> --- llvm/trunk/test/CodeGen/X86/vec_ext_inreg.ll (added)
> +++ llvm/trunk/test/CodeGen/X86/vec_ext_inreg.ll Fri Dec 11 15:31:27
> 2009
> @@ -0,0 +1,37 @@
> +; RUN: llc < %s -march=x86-64
> +
> +define <8 x i32> @a(<8 x i32> %a) nounwind {
> +  %b = trunc <8 x i32> %a to <8 x i16>
> +  %c = sext <8 x i16> %b to <8 x i32>
> +  ret <8 x i32> %c
> +}
> +
> +define <3 x i32> @b(<3 x i32> %a) nounwind {
> +  %b = trunc <3 x i32> %a to <3 x i16>
> +  %c = sext <3 x i16> %b to <3 x i32>
> +  ret <3 x i32> %c
> +}
> +
> +define <1 x i32> @c(<1 x i32> %a) nounwind {
> +  %b = trunc <1 x i32> %a to <1 x i16>
> +  %c = sext <1 x i16> %b to <1 x i32>
> +  ret <1 x i32> %c
> +}
> +
> +define <8 x i32> @d(<8 x i32> %a) nounwind {
> +  %b = trunc <8 x i32> %a to <8 x i16>
> +  %c = zext <8 x i16> %b to <8 x i32>
> +  ret <8 x i32> %c
> +}
> +
> +define <3 x i32> @e(<3 x i32> %a) nounwind {
> +  %b = trunc <3 x i32> %a to <3 x i16>
> +  %c = zext <3 x i16> %b to <3 x i32>
> +  ret <3 x i32> %c
> +}
> +
> +define <1 x i32> @f(<1 x i32> %a) nounwind {
> +  %b = trunc <1 x i32> %a to <1 x i16>
> +  %c = zext <1 x i16> %b to <1 x i32>
> +  ret <1 x i32> %c
> +}
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

-------------- next part --------------
A non-text attachment was scrubbed...
Name: loads-custom.bc
Type: application/octet-stream
Size: 2268 bytes
Desc: loads-custom.bc
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20091214/fedf58cf/attachment.obj>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: loads-custom.ll
Type: application/octet-stream
Size: 12799 bytes
Desc: loads-custom.ll
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20091214/fedf58cf/attachment-0001.obj>


More information about the llvm-commits mailing list