[llvm-commits] [llvm] r91053 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

[Jim Grosbach]

Author: grosbach
Date: Thu Dec 10 12:35:32 2009
New Revision: 91053

URL: http://llvm.org/viewvc/llvm-project?rev=91053&view=rev
Log:
Add instruction encoding for DMB/DSB

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=91053&r1=91052&r2=91053&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Dec 10 12:35:32 2009
@@ -1574,18 +1574,26 @@
 //
 
 // memory barriers protect the atomic sequences
-let isBarrier = 1 in {
+let isBarrier = 1, isPredicable = 0 in {
 def Int_MemBarrierV7 : AI<(outs), (ins),
                         Pseudo, NoItinerary,
                         "dmb", "",
                         [(ARMMemBarrier)]>,
-                        Requires<[HasV7]>;
+                        Requires<[HasV7]> {
+  let Inst{31-4} = 0xf57ff05;
+  // FIXME: add support for options other than a full system DMB
+  let Inst{3-0} = 0b1111;
+}
 
 def Int_SyncBarrierV7 : AI<(outs), (ins),
                         Pseudo, NoItinerary,
                         "dsb", "",
                         [(ARMSyncBarrier)]>,
-                        Requires<[HasV7]>;
+                        Requires<[HasV7]> {
+  let Inst{31-4} = 0xf57ff04;
+  // FIXME: add support for options other than a full system DSB
+  let Inst{3-0} = 0b1111;
+}
 }
 
 //===----------------------------------------------------------------------===//