[llvm-commits] [PATCH] More Spill Annotations

[Evan Cheng]

On Nov 24, 2009, at 6:29 AM, David Greene wrote:

> On Monday 23 November 2009 21:04, Evan Cheng wrote:
> 
>>> To do isVectorInstr and isVectorOperandInstr will require some additional
>>> flags in the .td files, I think.  Is that ok?  I don't want to to a whole
>>> bunch of work to find out later that there's a better way.
>> 
>> What kind of flags? These are fairly target specific information so I don't
>> think we want to add anything target independent. Can you enhance asm
>> printer so targets can inject target specific comments?
> 
> I was thinking of doing this by having TableGen infer isVector flags on
> instructions and operands from the type.  If an operand has a vector type,
> set the isVector flag on the operand.  If an instruction has any operands
> with isVector set, set isVector on the instruction.  The user can then 
> override these assumptions in the .td file by setting "let scalar=1" or
> "let vector=1."

That's reasonable. But I think we should let tablegen infer a lot more information. For every instruction with matching pattern it should save the SDNode opcode. So for ADD64*, ADDPS*, etc. we know they are all ISD::ADD instructions. Similarly we can save the ValueType information and infer properties such as isVector.

Such information will let codegen do all kinds of interesting optimizations and give us some truly rich asm comments.

> 
> I'm not sure how target-specific comments would work.  Do you have an
> example in mind?  I want to avoid having to mark every vector instruction as 
> the information can be inferred for 90% of the cases.

I am not sure either. It seems to me you are adding asm comments that many targets might not care about. Perhaps tablegen can infer some information and  attach it as asm comment string to each TargetInstrDesc entry?

Evan

> 
>                             -Dave