[llvm-commits] [llvm] r89684 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td
Johnny Chen
johnny.chen at apple.com
Mon Nov 23 13:03:11 PST 2009
Hi Bob,
Removal of N3VImm and N2VDup is done.
The N2VImm thing is more involved and the current specification looks fine, so I dare not touch it. :-)
On Nov 23, 2009, at 11:40 AM, Bob Wilson wrote:
> Very nice! Thanks for doing this.
>
> Can you do the same thing for r84572 (remove N3VImm) and r84730 (remove N2VDup and associated changes)? You might also consider changing the shift-operand and N2VImm portions of r84730, but I'll leave that to your discretion.
>
> On Nov 23, 2009, at 10:16 AM, Johnny Chen wrote:
>
>> Author: johnny
>> Date: Mon Nov 23 12:16:16 2009
>> New Revision: 89684
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=89684&view=rev
>> Log:
>> Partially revert r89377 by removing NLdStLN class definition from
>> ARMInstrFormats.td and fixing VLD[234]LN* and VST[234]LN* to derive from NLdSt
>> instead of NLdStLN.
>>
>> Modified:
>> llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=89684&r1=89683&r2=89684&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Nov 23 12:16:16 2009
>> @@ -1248,17 +1248,6 @@
>> let Inst{7-4} = op7_4;
>> }
>>
>> -// With selective bit(s) from op7_4 specified by subclasses.
>> -class NLdStLN<bit op23, bits<2> op21_20, bits<4> op11_8,
>> - dag oops, dag iops, InstrItinClass itin,
>> - string opc, string asm, string cstr, list<dag> pattern>
>> - : NeonI<oops, iops, AddrMode6, IndexModeNone, itin, opc, asm, cstr, pattern> {
>> - let Inst{31-24} = 0b11110100;
>> - let Inst{23} = op23;
>> - let Inst{21-20} = op21_20;
>> - let Inst{11-8} = op11_8;
>> -}
>> -
>> class NDataI<dag oops, dag iops, InstrItinClass itin,
>> string opc, string asm, string cstr, list<dag> pattern>
>> : NeonI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm,
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=89684&r1=89683&r2=89684&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Nov 23 12:16:16 2009
>> @@ -280,11 +280,11 @@
>>
>> // VLD2LN : Vector Load (single 2-element structure to one lane)
>> class VLD2LN<bits<4> op11_8, string OpcodeStr>
>> - : NLdStLN<1,0b10,op11_8, (outs DPR:$dst1, DPR:$dst2),
>> - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
>> - IIC_VLD2,
>> - OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr",
>> - "$src1 = $dst1, $src2 = $dst2", []>;
>> + : NLdSt<1,0b10,op11_8,{?,?,?,?}, (outs DPR:$dst1, DPR:$dst2),
>> + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
>> + IIC_VLD2,
>> + OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr",
>> + "$src1 = $dst1, $src2 = $dst2", []>;
>>
>> // vld2 to single-spaced registers.
>> def VLD2LNd8 : VLD2LN<0b0001, "vld2.8">;
>> @@ -313,12 +313,12 @@
>>
>> // VLD3LN : Vector Load (single 3-element structure to one lane)
>> class VLD3LN<bits<4> op11_8, string OpcodeStr>
>> - : NLdStLN<1,0b10,op11_8, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
>> - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
>> - nohash_imm:$lane), IIC_VLD3,
>> - OpcodeStr,
>> - "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr",
>> - "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
>> + : NLdSt<1,0b10,op11_8,{?,?,?,?}, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
>> + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
>> + nohash_imm:$lane), IIC_VLD3,
>> + OpcodeStr,
>> + "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr",
>> + "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
>>
>> // vld3 to single-spaced registers.
>> def VLD3LNd8 : VLD3LN<0b0010, "vld3.8"> {
>> @@ -349,13 +349,13 @@
>>
>> // VLD4LN : Vector Load (single 4-element structure to one lane)
>> class VLD4LN<bits<4> op11_8, string OpcodeStr>
>> - : NLdStLN<1,0b10,op11_8,
>> - (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
>> - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
>> - nohash_imm:$lane), IIC_VLD4,
>> - OpcodeStr,
>> - "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr",
>> - "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
>> + : NLdSt<1,0b10,op11_8,{?,?,?,?},
>> + (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
>> + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
>> + nohash_imm:$lane), IIC_VLD4,
>> + OpcodeStr,
>> + "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr",
>> + "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
>>
>> // vld4 to single-spaced registers.
>> def VLD4LNd8 : VLD4LN<0b0011, "vld4.8">;
>> @@ -504,11 +504,11 @@
>>
>> // VST2LN : Vector Store (single 2-element structure from one lane)
>> class VST2LN<bits<4> op11_8, string OpcodeStr>
>> - : NLdStLN<1,0b00,op11_8, (outs),
>> - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
>> - IIC_VST,
>> - OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr",
>> - "", []>;
>> + : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
>> + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
>> + IIC_VST,
>> + OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr",
>> + "", []>;
>>
>> // vst2 to single-spaced registers.
>> def VST2LNd8 : VST2LN<0b0001, "vst2.8">;
>> @@ -537,11 +537,11 @@
>>
>> // VST3LN : Vector Store (single 3-element structure from one lane)
>> class VST3LN<bits<4> op11_8, string OpcodeStr>
>> - : NLdStLN<1,0b00,op11_8, (outs),
>> - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
>> - nohash_imm:$lane), IIC_VST,
>> - OpcodeStr,
>> - "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr", "", []>;
>> + : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
>> + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
>> + nohash_imm:$lane), IIC_VST,
>> + OpcodeStr,
>> + "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr", "", []>;
>>
>> // vst3 to single-spaced registers.
>> def VST3LNd8 : VST3LN<0b0010, "vst3.8"> {
>> @@ -572,12 +572,12 @@
>>
>> // VST4LN : Vector Store (single 4-element structure from one lane)
>> class VST4LN<bits<4> op11_8, string OpcodeStr>
>> - : NLdStLN<1,0b00,op11_8, (outs),
>> - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
>> - nohash_imm:$lane), IIC_VST,
>> - OpcodeStr,
>> - "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr",
>> - "", []>;
>> + : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
>> + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
>> + nohash_imm:$lane), IIC_VST,
>> + OpcodeStr,
>> + "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr",
>> + "", []>;
>>
>> // vst4 to single-spaced registers.
>> def VST4LNd8 : VST4LN<0b0011, "vst4.8">;
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
More information about the llvm-commits
mailing list