[llvm-commits] [llvm] r89699 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td

[Bob Wilson]

Thanks!

On Nov 23, 2009, at 1:00 PM, Johnny Chen wrote:

> Author: johnny
> Date: Mon Nov 23 15:00:43 2009
> New Revision: 89699
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=89699&view=rev
> Log:
> Partially revert r84730 by removing N2VDup from ARMInstrFormats.td and modifying
> VDUPLND and VDUPLNQ to derive from N2V instead of N2VDup.  VDUPLND and VDUPLNQ
> now expect op19_18 and op17_16 as the first two args.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=89699&r1=89698&r2=89699&view=diff
> 
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Nov 23 15:00:43 2009
> @@ -1285,19 +1285,6 @@
>   let Inst{4} = op4;
> }
> 
> -// NEON Vector Duplicate (scalar).
> -// Inst{19-16} is specified by subclasses.
> -class N2VDup<bits<2> op24_23, bits<2> op21_20, bits<5> op11_7, bit op6, bit op4,
> -             dag oops, dag iops, InstrItinClass itin,
> -             string opc, string asm, string cstr, list<dag> pattern>
> -  : NDataI<oops, iops, itin, opc, asm, cstr, pattern> {
> -  let Inst{24-23} = op24_23;
> -  let Inst{21-20} = op21_20;
> -  let Inst{11-7} = op11_7;
> -  let Inst{6} = op6;
> -  let Inst{4} = op4;
> -}
> -
> // NEON 2 vector register with immediate.
> class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
>              dag oops, dag iops, InstrItinClass itin,
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=89699&r1=89698&r2=89699&view=diff
> 
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Nov 23 15:00:43 2009
> @@ -2682,28 +2682,29 @@
> 
> //   VDUP     : Vector Duplicate Lane (from scalar to all elements)
> 
> -class VDUPLND<string OpcodeStr, ValueType Ty>
> -  : N2VDup<0b11, 0b11, 0b11000, 0, 0,
> +class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
> +  : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
>         (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
>         OpcodeStr, "\t$dst, $src[$lane]", "",
>         [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
> 
> -class VDUPLNQ<string OpcodeStr, ValueType ResTy, ValueType OpTy>
> -  : N2VDup<0b11, 0b11, 0b11000, 1, 0,
> +class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
> +              ValueType ResTy, ValueType OpTy>
> +  : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
>         (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
>         OpcodeStr, "\t$dst, $src[$lane]", "",
>         [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
> 
> // Inst{19-16} is partially specified depending on the element size.
> 
> -def VDUPLN8d  : VDUPLND<"vdup.8", v8i8> { let Inst{16} = 1; }
> -def VDUPLN16d : VDUPLND<"vdup.16", v4i16> { let Inst{17-16} = 0b10; }
> -def VDUPLN32d : VDUPLND<"vdup.32", v2i32> { let Inst{18-16} = 0b100; }
> -def VDUPLNfd  : VDUPLND<"vdup.32", v2f32> { let Inst{18-16} = 0b100; }
> -def VDUPLN8q  : VDUPLNQ<"vdup.8", v16i8, v8i8> { let Inst{16} = 1; }
> -def VDUPLN16q : VDUPLNQ<"vdup.16", v8i16, v4i16> { let Inst{17-16} = 0b10; }
> -def VDUPLN32q : VDUPLNQ<"vdup.32", v4i32, v2i32> { let Inst{18-16} = 0b100; }
> -def VDUPLNfq  : VDUPLNQ<"vdup.32", v4f32, v2f32> { let Inst{18-16} = 0b100; }
> +def VDUPLN8d  : VDUPLND<{?,?}, {?,1}, "vdup.8", v8i8>;
> +def VDUPLN16d : VDUPLND<{?,?}, {1,0}, "vdup.16", v4i16>;
> +def VDUPLN32d : VDUPLND<{?,1}, {0,0}, "vdup.32", v2i32>;
> +def VDUPLNfd  : VDUPLND<{?,1}, {0,0}, "vdup.32", v2f32>;
> +def VDUPLN8q  : VDUPLNQ<{?,?}, {?,1}, "vdup.8", v16i8, v8i8>;
> +def VDUPLN16q : VDUPLNQ<{?,?}, {1,0}, "vdup.16", v8i16, v4i16>;
> +def VDUPLN32q : VDUPLNQ<{?,1}, {0,0}, "vdup.32", v4i32, v2i32>;
> +def VDUPLNfq  : VDUPLNQ<{?,1}, {0,0}, "vdup.32", v4f32, v2f32>;
> 
> def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
>           (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
> @@ -2722,19 +2723,15 @@
>                                    (DSubReg_i32_reg imm:$lane))),
>                            (SubReg_i32_lane imm:$lane)))>;
> 
> -def  VDUPfdf  : N2VDup<0b11, 0b11, 0b11000, 0, 0,
> -                       (outs DPR:$dst), (ins SPR:$src),
> -                       IIC_VMOVD, "vdup.32", "\t$dst, ${src:lane}", "",
> -                       [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]> {
> -  let Inst{18-16} = 0b100;
> -}
> -
> -def  VDUPfqf  : N2VDup<0b11, 0b11, 0b11000, 1, 0,
> -                       (outs QPR:$dst), (ins SPR:$src),
> -                       IIC_VMOVD, "vdup.32", "\t$dst, ${src:lane}", "",
> -                       [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]> {
> -  let Inst{18-16} = 0b100;
> -}
> +def  VDUPfdf  : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 0, 0,
> +                    (outs DPR:$dst), (ins SPR:$src),
> +                    IIC_VMOVD, "vdup.32", "\t$dst, ${src:lane}", "",
> +                    [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
> +
> +def  VDUPfqf  : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 1, 0,
> +                    (outs QPR:$dst), (ins SPR:$src),
> +                    IIC_VMOVD, "vdup.32", "\t$dst, ${src:lane}", "",
> +                    [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
> 
> def : Pat<(v2i64 (NEONvduplane (v2i64 QPR:$src), imm:$lane)),
>           (INSERT_SUBREG QPR:$src, 
> 
> 
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