[llvm-commits] [llvm] r89491 - in /llvm/trunk: include/llvm/IntrinsicsX86.td lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/palignr-2.ll
Sean Callanan
scallanan at apple.com
Fri Nov 20 14:06:50 PST 2009
Looks like I broke the clang testsuite. Reverting.
Seam
On Nov 20, 2009, at 1:40 PM, Sean Callanan wrote:
> Author: spyffe
> Date: Fri Nov 20 15:40:28 2009
> New Revision: 89491
>
> URL: http://llvm.org/viewvc/llvm-project?rev=89491&view=rev
> Log:
> Fixed PALIGNR to take 8-bit rotations in all cases.
> Also fixed the corresponding testcase, and the PALIGNR
> intrinsic (tested for correctness with llvm-gcc).
>
> Modified:
> llvm/trunk/include/llvm/IntrinsicsX86.td
> llvm/trunk/lib/Target/X86/X86InstrSSE.td
> llvm/trunk/test/CodeGen/X86/palignr-2.ll
>
> Modified: llvm/trunk/include/llvm/IntrinsicsX86.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=89491&r1=89490&r2=89491&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/include/llvm/IntrinsicsX86.td (original)
> +++ llvm/trunk/include/llvm/IntrinsicsX86.td Fri Nov 20 15:40:28 2009
> @@ -673,10 +673,10 @@
> let TargetPrefix = "x86" in { // All intrinsics start with
> "llvm.x86.".
> def int_x86_ssse3_palign_r :
> GCCBuiltin<"__builtin_ia32_palignr">,
> Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty,
> - llvm_v1i64_ty, llvm_i16_ty], [IntrNoMem]>;
> + llvm_v1i64_ty, llvm_i8_ty], [IntrNoMem]>;
> def int_x86_ssse3_palign_r_128 :
> GCCBuiltin<"__builtin_ia32_palignr128">,
> Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty,
> - llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
> + llvm_v2i64_ty, llvm_i8_ty], [IntrNoMem]>;
> }
>
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=89491&r1=89490&r2=89491&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Nov 20 15:40:28 2009
> @@ -2820,40 +2820,40 @@
>
> let Constraints = "$src1 = $dst" in {
> def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
> - (ins VR64:$src1, VR64:$src2, i16imm:
> $src3),
> + (ins VR64:$src1, VR64:$src2, i8imm:$src3),
> "palignr\t{$src3, $src2, $dst|$dst,
> $src2, $src3}",
> []>;
> def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
> - (ins VR64:$src1, i64mem:$src2, i16imm:
> $src3),
> + (ins VR64:$src1, i64mem:$src2, i8imm:
> $src3),
> "palignr\t{$src3, $src2, $dst|$dst,
> $src2, $src3}",
> []>;
>
> def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
> - (ins VR128:$src1, VR128:$src2, i32imm:
> $src3),
> + (ins VR128:$src1, VR128:$src2, i8imm:
> $src3),
> "palignr\t{$src3, $src2, $dst|$dst,
> $src2, $src3}",
> []>, OpSize;
> def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
> - (ins VR128:$src1, i128mem:$src2, i32imm:
> $src3),
> + (ins VR128:$src1, i128mem:$src2, i8imm:
> $src3),
> "palignr\t{$src3, $src2, $dst|$dst,
> $src2, $src3}",
> []>, OpSize;
> }
>
> // palignr patterns.
> -def : Pat<(int_x86_ssse3_palign_r VR64:$src1, VR64:$src2, (i16 imm:
> $src3)),
> +def : Pat<(int_x86_ssse3_palign_r VR64:$src1, VR64:$src2, (i8 imm:
> $src3)),
> (PALIGNR64rr VR64:$src1, VR64:$src2, (BYTE_imm imm:$src3))>,
> Requires<[HasSSSE3]>;
> def : Pat<(int_x86_ssse3_palign_r VR64:$src1,
> (memop64 addr:$src2),
> - (i16 imm:$src3)),
> + (i8 imm:$src3)),
> (PALIGNR64rm VR64:$src1, addr:$src2, (BYTE_imm imm:$src3))>,
> Requires<[HasSSSE3]>;
>
> -def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, VR128:$src2,
> (i32 imm:$src3)),
> +def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, VR128:$src2, (i8
> imm:$src3)),
> (PALIGNR128rr VR128:$src1, VR128:$src2, (BYTE_imm imm:
> $src3))>,
> Requires<[HasSSSE3]>;
> def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1,
> (memopv2i64 addr:$src2),
> - (i32 imm:$src3)),
> + (i8 imm:$src3)),
> (PALIGNR128rm VR128:$src1, addr:$src2, (BYTE_imm imm:
> $src3))>,
> Requires<[HasSSSE3]>;
>
>
> Modified: llvm/trunk/test/CodeGen/X86/palignr-2.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/palignr-2.ll?rev=89491&r1=89490&r2=89491&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/palignr-2.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/palignr-2.ll Fri Nov 20 15:40:28 2009
> @@ -9,12 +9,12 @@
> entry:
> ; CHECK: t1:
> ; palignr $3, %xmm1, %xmm0
> - %0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>
> %a, <2 x i64> %b, i32 24) nounwind readnone
> + %0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>
> %a, <2 x i64> %b, i8 24) nounwind readnone
> store <2 x i64> %0, <2 x i64>* bitcast ([4 x i32]* @c to <2 x
> i64>*), align 16
> ret void
> }
>
> -declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x
> i64>, i32) nounwind readnone
> +declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x
> i64>, i8) nounwind readnone
>
> define void @t2() nounwind ssp {
> entry:
> @@ -22,7 +22,7 @@
> ; palignr $4, _b, %xmm0
> %0 = load <2 x i64>* bitcast ([4 x i32]* @b to <2 x i64>*), align
> 16 ; <<2 x i64>> [#uses=1]
> %1 = load <2 x i64>* bitcast ([4 x i32]* @a to <2 x i64>*), align
> 16 ; <<2 x i64>> [#uses=1]
> - %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>
> %1, <2 x i64> %0, i32 32) nounwind readnone
> + %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>
> %1, <2 x i64> %0, i8 32) nounwind readnone
> store <2 x i64> %2, <2 x i64>* bitcast ([4 x i32]* @c to <2 x
> i64>*), align 16
> ret void
> }
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
More information about the llvm-commits
mailing list