[llvm-commits] [llvm] r87060 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/Target/PowerPC/PPCISelLowering.cpp test/CodeGen/PowerPC/vec_splat_constant.ll
Dale Johannesen
dalej at apple.com
Thu Nov 12 17:45:18 PST 2009
Author: johannes
Date: Thu Nov 12 19:45:18 2009
New Revision: 87060
URL: http://llvm.org/viewvc/llvm-project?rev=87060&view=rev
Log:
Adjust isConstantSplat to allow for big-endian targets.
PPC is such a target; make it work.
Added:
llvm/trunk/test/CodeGen/PowerPC/vec_splat_constant.ll
Modified:
llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=87060&r1=87059&r2=87060&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Thu Nov 12 19:45:18 2009
@@ -1953,10 +1953,10 @@
/// that value are zero, and the corresponding bits in the SplatUndef mask
/// are set. The SplatBitSize value is set to the splat element size in
/// bits. HasAnyUndefs is set to true if any bits in the vector are
- /// undefined.
+ /// undefined. isBigEndian describes the endianness of the target.
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef,
unsigned &SplatBitSize, bool &HasAnyUndefs,
- unsigned MinSplatBits = 0);
+ unsigned MinSplatBits = 0, bool isBigEndian = false);
static inline bool classof(const BuildVectorSDNode *) { return true; }
static inline bool classof(const SDNode *N) {
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=87060&r1=87059&r2=87060&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Nov 12 19:45:18 2009
@@ -5916,7 +5916,8 @@
APInt &SplatUndef,
unsigned &SplatBitSize,
bool &HasAnyUndefs,
- unsigned MinSplatBits) {
+ unsigned MinSplatBits,
+ bool isBigEndian) {
EVT VT = getValueType(0);
assert(VT.isVector() && "Expected a vector type");
unsigned sz = VT.getSizeInBits();
@@ -5933,12 +5934,14 @@
unsigned int nOps = getNumOperands();
assert(nOps > 0 && "isConstantSplat has 0-size build vector");
unsigned EltBitSize = VT.getVectorElementType().getSizeInBits();
- for (unsigned i = 0; i < nOps; ++i) {
+
+ for (unsigned j = 0; j < nOps; ++j) {
+ unsigned i = isBigEndian ? nOps-1-j : j;
SDValue OpVal = getOperand(i);
- unsigned BitPos = i * EltBitSize;
+ unsigned BitPos = j * EltBitSize;
if (OpVal.getOpcode() == ISD::UNDEF)
- SplatUndef |= APInt::getBitsSet(sz, BitPos, BitPos +EltBitSize);
+ SplatUndef |= APInt::getBitsSet(sz, BitPos, BitPos + EltBitSize);
else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal))
SplatValue |= (APInt(CN->getAPIntValue()).zextOrTrunc(EltBitSize).
zextOrTrunc(sz) << BitPos);
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=87060&r1=87059&r2=87060&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Nov 12 19:45:18 2009
@@ -637,7 +637,7 @@
unsigned BitSize;
bool HasAnyUndefs;
- if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32))
+ if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
return CFP->getValueAPF().isNegZero();
@@ -3672,7 +3672,7 @@
unsigned SplatBitSize;
bool HasAnyUndefs;
if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
- HasAnyUndefs) || SplatBitSize > 32)
+ HasAnyUndefs, 0, true) || SplatBitSize > 32)
return SDValue();
unsigned SplatBits = APSplatBits.getZExtValue();
Added: llvm/trunk/test/CodeGen/PowerPC/vec_splat_constant.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_splat_constant.ll?rev=87060&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_splat_constant.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_splat_constant.ll Thu Nov 12 19:45:18 2009
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mcpu=g5 | FileCheck %s
+; Formerly incorrectly inserted vsldoi (endian confusion)
+
+ at baz = common global <16 x i8> zeroinitializer ; <<16 x i8>*> [#uses=1]
+
+define void @foo(<16 x i8> %x) nounwind ssp {
+entry:
+; CHECK: _foo:
+; CHECK-NOT: vsldoi
+ %x_addr = alloca <16 x i8> ; <<16 x i8>*> [#uses=2]
+ %temp = alloca <16 x i8> ; <<16 x i8>*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store <16 x i8> %x, <16 x i8>* %x_addr
+ store <16 x i8> <i8 0, i8 0, i8 0, i8 14, i8 0, i8 0, i8 0, i8 14, i8 0, i8 0, i8 0, i8 14, i8 0, i8 0, i8 0, i8 14>, <16 x i8>* %temp, align 16
+ %0 = load <16 x i8>* %x_addr, align 16 ; <<16 x i8>> [#uses=1]
+ %1 = load <16 x i8>* %temp, align 16 ; <<16 x i8>> [#uses=1]
+ %tmp = add <16 x i8> %0, %1 ; <<16 x i8>> [#uses=1]
+ store <16 x i8> %tmp, <16 x i8>* @baz, align 16
+ br label %return
+
+return: ; preds = %entry
+ ret void
+; CHECK: blr
+}
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